diff options
| author | Nick Foster <nick@ettus.com> | 2012-01-12 11:03:43 -0800 |
|---|---|---|
| committer | Josh Blum <josh@joshknows.com> | 2012-02-01 10:04:53 -0800 |
| commit | 081714b4ce40701067e5513127dd9b9322cbfa5d (patch) | |
| tree | c5569358b623e1abfe2222b0fe2473aec0506c5d /firmware/fx2/b100/usrp_regs.h | |
| parent | 81b4689cf5a16b71c85b4a0f94746d61091fa29f (diff) | |
| download | uhd-081714b4ce40701067e5513127dd9b9322cbfa5d.tar.gz uhd-081714b4ce40701067e5513127dd9b9322cbfa5d.tar.bz2 uhd-081714b4ce40701067e5513127dd9b9322cbfa5d.zip | |
B100 firmware changes to allow slave mode TX/RX.
Diffstat (limited to 'firmware/fx2/b100/usrp_regs.h')
| -rw-r--r-- | firmware/fx2/b100/usrp_regs.h | 28 |
1 files changed, 0 insertions, 28 deletions
diff --git a/firmware/fx2/b100/usrp_regs.h b/firmware/fx2/b100/usrp_regs.h index f6695d9f9..3d65337f5 100644 --- a/firmware/fx2/b100/usrp_regs.h +++ b/firmware/fx2/b100/usrp_regs.h @@ -41,8 +41,6 @@ #define bmALTERA_NCONFIG bmBIT1 #define bmALTERA_DATA0 bmBIT3 #define bmALTERA_NSTATUS bmBIT4 -#define bmRESET_FPGA_FIFOS bmBIT7 - #define bmALTERA_BITS (bmALTERA_DCLK \ | bmALTERA_NCONFIG \ @@ -64,7 +62,6 @@ sbit at PORT_A_ADDR+0 bitALTERA_DCLK; // 0x80 is the bit address of PORT A sbit at PORT_A_ADDR+1 bitALTERA_NCONFIG; sbit at PORT_A_ADDR+3 bitALTERA_DATA0; -sbit at PORT_A_ADDR+6 bitSHORT_PACKET_SIGNAL; sbit at PORT_C_ADDR+7 bitALTERA_CONF_DONE; @@ -102,29 +99,4 @@ sbit at PORT_C_ADDR+7 bitALTERA_CONF_DONE; #define bmPORT_E_OUTPUTS (0) #define bmPORT_E_INITIAL (0) -/* - * FPGA output lines that are tied to FX2 RDYx inputs. - * These are readable using GPIFREADYSTAT. - */ -//#define bmFPGA_HAS_SPACE bmBIT0 // usbrdy[0] has room for 512 byte packet -//#define bmFPGA_PKT_AVAIL bmBIT1 // usbrdy[1] has >= 512 bytes available - -#define bmDATA_EMPTY bmBIT0 //data output FIFO has no data ready -#define bmDATA_FIFO_FULL bmBIT1 //data input FIFO is full -#define bmCTRL_EMPTY bmBIT2 //control output FIFO has no data ready -#define bmCTRL_FIFO_FULL bmBIT3 //control input FIFO is full - -// #define bmTX_UNDERRUN bmBIT2 // usbrdy[2] D/A ran out of data -// #define bmRX_OVERRUN bmBIT3 // usbrdy[3] A/D ran out of buffer - -/* - * FPGA input lines that are tied to the FX2 CTLx outputs. - * - * These are controlled by the GPIF microprogram... - */ -// WE bmBIT0 // usbctl[0] write enable -// RE bmBIT1 // usbctl[1] read enable -// OE bmBIT2 // usbctl[2] output enable -// EP bmBIT3 // usbctl[3] endpoint select (data/ctrl) - #endif /* _USRP_REV1_REGS_H_ */ |