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| author | Josh Blum <josh@joshknows.com> | 2012-08-31 11:20:17 -0700 |
|---|---|---|
| committer | Josh Blum <josh@joshknows.com> | 2012-08-31 11:20:17 -0700 |
| commit | 667dcf0b98bb5a99654cf883fb97d2a549582cff (patch) | |
| tree | 7c845d7ac3f506c000ab495b1d62d976b816b5cd /firmware/fx2/b100/usrp_common.c | |
| parent | 05a06254a7f0149425bdda0e5544507bd35a671b (diff) | |
| parent | 36a7def9aa6cecaa6f3cbf9979544d6fd5848a08 (diff) | |
| download | uhd-667dcf0b98bb5a99654cf883fb97d2a549582cff.tar.gz uhd-667dcf0b98bb5a99654cf883fb97d2a549582cff.tar.bz2 uhd-667dcf0b98bb5a99654cf883fb97d2a549582cff.zip | |
Merge branch 'next'
Diffstat (limited to 'firmware/fx2/b100/usrp_common.c')
| -rw-r--r-- | firmware/fx2/b100/usrp_common.c | 12 |
1 files changed, 9 insertions, 3 deletions
diff --git a/firmware/fx2/b100/usrp_common.c b/firmware/fx2/b100/usrp_common.c index a21353688..968b03d48 100644 --- a/firmware/fx2/b100/usrp_common.c +++ b/firmware/fx2/b100/usrp_common.c @@ -85,8 +85,8 @@ init_usrp (void) // set autoin length for EP6/EP8 EP6AUTOINLENH = (512) >> 8; SYNCDELAY; // this is the length for high speed EP6AUTOINLENL = (512) & 0xff; SYNCDELAY; - EP8AUTOINLENH = (32) >> 8; SYNCDELAY; - EP8AUTOINLENL = (32) & 0xff; SYNCDELAY; + EP8AUTOINLENH = (512) >> 8; SYNCDELAY; + EP8AUTOINLENL = (512) & 0xff; SYNCDELAY; //set FLAGA, FLAGB, FLAGC, FLAGD to be EP2EF, EP4EF, EP6PF, EP8PF PINFLAGSAB = (bmEP2EF) | (bmEP4EF << 4); @@ -99,13 +99,19 @@ init_usrp (void) EP6FIFOPFL = 0xFD; SYNCDELAY; + EP8FIFOPFH = 0x09; + SYNCDELAY; + EP8FIFOPFL = 0xFD; + SYNCDELAY; + // EP2FIFOPFH = 0x08; // SYNCDELAY; // EP2FIFOPFL = 0x00; // SYNCDELAY; //assert FIFOEMPTY one cycle sooner so we get it in time at the FPGA - EP2FIFOCFG |= bmBIT5; + EP2FIFOCFG |= bmBIT5; + EP4FIFOCFG |= bmBIT5; //set FIFOPINPOLAR to normal (active low) mode FIFOPINPOLAR = 0x00; |