diff options
| author | Nick Foster <nick@ettus.com> | 2012-01-12 11:03:43 -0800 |
|---|---|---|
| committer | Josh Blum <josh@joshknows.com> | 2012-02-01 10:04:53 -0800 |
| commit | 081714b4ce40701067e5513127dd9b9322cbfa5d (patch) | |
| tree | c5569358b623e1abfe2222b0fe2473aec0506c5d /firmware/fx2/b100/usrp_common.c | |
| parent | 81b4689cf5a16b71c85b4a0f94746d61091fa29f (diff) | |
| download | uhd-081714b4ce40701067e5513127dd9b9322cbfa5d.tar.gz uhd-081714b4ce40701067e5513127dd9b9322cbfa5d.tar.bz2 uhd-081714b4ce40701067e5513127dd9b9322cbfa5d.zip | |
B100 firmware changes to allow slave mode TX/RX.
Diffstat (limited to 'firmware/fx2/b100/usrp_common.c')
| -rw-r--r-- | firmware/fx2/b100/usrp_common.c | 17 |
1 files changed, 9 insertions, 8 deletions
diff --git a/firmware/fx2/b100/usrp_common.c b/firmware/fx2/b100/usrp_common.c index 4b6dde881..7aedce9f7 100644 --- a/firmware/fx2/b100/usrp_common.c +++ b/firmware/fx2/b100/usrp_common.c @@ -32,12 +32,11 @@ init_usrp (void) CPUCS = bmCLKSPD1; // CPU runs @ 48 MHz CKCON = 0; // MOVX takes 2 cycles - // IFCLK is generated internally and runs at 48 MHz; GPIF "master mode" - - IFCONFIG = bmIFCLKSRC | bm3048MHZ | bmIFCLKOE | bmIFCLKPOL | bmIFGPIF; + // IFCLK is generated internally and runs at 48 MHz; slave FIFO mode + IFCONFIG = bmIFCLKSRC | bm3048MHZ | bmIFCLKOE | bmIFSLAVE; SYNCDELAY; - // configure IO ports (B and D are used by GPIF) + // configure IO ports (B and D are used by slave FIFO) IOA = bmPORT_A_INITIAL; // Port A initial state OEA = bmPORT_A_OUTPUTS; // Port A direction register @@ -77,23 +76,25 @@ init_usrp (void) EP2FIFOCFG = bmWORDWIDE; SYNCDELAY; EP2FIFOCFG = bmAUTOOUT | bmWORDWIDE; SYNCDELAY; - EP6FIFOCFG = bmZEROLENIN | bmWORDWIDE; SYNCDELAY; + EP6FIFOCFG = bmZEROLENIN | bmWORDWIDE; SYNCDELAY; + EP6FIFOCFG = bmZEROLENIN | bmAUTOIN | bmWORDWIDE; SYNCDELAY; //EP6FIFOCFG = bmWORDWIDE; SYNCDELAY; EP4FIFOCFG = bmWORDWIDE; SYNCDELAY; EP4FIFOCFG = bmAUTOOUT | bmWORDWIDE; SYNCDELAY; - EP8FIFOCFG = bmAUTOIN | bmWORDWIDE; SYNCDELAY; + EP8FIFOCFG = bmZEROLENIN | bmWORDWIDE; SYNCDELAY; + EP8FIFOCFG = bmZEROLENIN | bmAUTOIN | bmWORDWIDE; SYNCDELAY; EP0BCH = 0; SYNCDELAY; // arm EP1OUT so we can receive "out" packets (TRM pg 8-8) EP1OUTBC = 0; SYNCDELAY; - +/* EP2GPIFFLGSEL = 0x00; SYNCDELAY; // For EP2OUT, GPIF uses EF flag EP6GPIFFLGSEL = 0x00; SYNCDELAY; // For EP6IN, GPIF uses FF flag EP4GPIFFLGSEL = 0x00; SYNCDELAY; EP8GPIFFLGSEL = 0x00; SYNCDELAY; - +*/ // set autoin length for EP6 // FIXME should be f(enumeration) |