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authorMoritz Fischer <moritz.fischer@ettus.com>2015-07-13 14:03:42 -0700
committerMoritz Fischer <moritz.fischer@ettus.com>2015-07-13 14:03:42 -0700
commitc65e0ea6e387b39e115b6af28e79ba1418f605b2 (patch)
tree85bc5673ca01f22b6b9362b0aba8c80d13ba1eab /firmware/e300/battery/adc.c
parent69bcfba936e49c2825a6d9be677c3150a5c6b70c (diff)
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e3xx: Added firmware for battery based devices.
Note: This firmware does *not* support Rev B units. Signed-off-by: Moritz Fischer <moritz.fischer@ettus.com>
Diffstat (limited to 'firmware/e300/battery/adc.c')
-rw-r--r--firmware/e300/battery/adc.c58
1 files changed, 58 insertions, 0 deletions
diff --git a/firmware/e300/battery/adc.c b/firmware/e300/battery/adc.c
new file mode 100644
index 000000000..998408066
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+++ b/firmware/e300/battery/adc.c
@@ -0,0 +1,58 @@
+/* USRP E310 Firmware Atmel AVR ADC driver
+ * Copyright (C) 2014 Ettus Research
+ * This file is part of the USRP E310 Firmware
+ * The USRP E310 Firmware is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 2 of the License, or
+ * (at your option) any later version.
+ * The USRP E310 Firmware is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ * You should have received a copy of the GNU General Public License
+ * along with the USRP E310 Firmware. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <avr/io.h>
+
+#include "adc.h"
+#include "utils.h"
+
+void adc_init(void)
+{
+ /* disable digital input on PC0 (ADC0) */
+ DIDR0 |= 0x1;
+
+ /* set to AVcc reference, left aligned and ADC0 */
+ ADMUX = (1 << REFS0)
+ | (0 << ADLAR)
+ | (0 << MUX0);
+
+ /* prescale clock by 128 */
+ ADCSRA = BIT(ADPS2) | BIT(ADPS1) | BIT(ADPS0);
+}
+
+uint16_t adc_single_shot(void)
+{
+ uint16_t value;
+
+ /* turn on ADC */
+ ADCSRA |= (1 << ADEN);
+
+ /* start conversion */
+ ADCSRA |= (1 << ADSC);
+
+ /* busy wait for conversion */
+ while (ADCSRA & (1 << ADSC)) {
+ };
+
+ /* we need to first read the lower bits,
+ * which will lock the value until higher bits are read */
+ value = (ADCL << 0);
+ value |= (ADCH << 8);
+
+ /* turn adc of again */
+ ADCSRA &= ~(1 << ADEN);
+
+ return value;
+}