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| author | Andrew Moch <Andrew.Moch@ni.com> | 2020-07-29 17:57:13 +0100 |
|---|---|---|
| committer | Wade Fife <wade.fife@ettus.com> | 2020-07-31 11:55:47 -0500 |
| commit | 6ef642e3ac44c52b98b124f30dc84b1683859989 (patch) | |
| tree | b6ff47d7b1cd939cbd26cf4c3142523e4964a4bc /firmware/README.md | |
| parent | 3beb450e2ab29e6021f4091fd1a3cc6522f994c4 (diff) | |
| download | uhd-6ef642e3ac44c52b98b124f30dc84b1683859989.tar.gz uhd-6ef642e3ac44c52b98b124f30dc84b1683859989.tar.bz2 uhd-6ef642e3ac44c52b98b124f30dc84b1683859989.zip | |
fpga: lib: Update AxiLiteIf
This fixes a bug on wrstb in AxiLiteIf and adds a new AxiLiteIf_v that
can be used to stitch onto Verilog port_maps.
Diffstat (limited to 'firmware/README.md')
0 files changed, 0 insertions, 0 deletions