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authorJohnathan Corgan <jcorgan@corganenterprises.com>2009-10-01 11:00:25 -0700
committerJohnathan Corgan <jcorgan@corganenterprises.com>2009-10-01 11:07:59 -0700
commit1ff74777e47f3a2edefc5154484f2bdcb86c1a13 (patch)
tree04f94ef4f7f06a210f7532592829332c7f2621f0 /eth/rtl/verilog/header.vh
parent7b8f65256b5ea300187ebb6a359df2fa707a295d (diff)
parent42fc55415af499980901c7787f44c7e74b4a9ce1 (diff)
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Merge branch 'new_eth' of http://gnuradio.org/git/matt into master
* 'new_eth' of http://gnuradio.org/git/matt: (42 commits) Fix warnings, mostly from implicitly defined wires or unspecified widths fullchip sim now compiles again, after moving eth and models over to new simple_gemac remove unused opencores remove debugging code no idea where this came from, it shouldn't be here Copied wb_1master back from quad radio Remove old mac. Good riddance. remove unused port More xilinx fifos, more clean up of our fifos might as well use a cascade fifo to help timing and give a little more capacity fix a typo which caused tx glitches Untested fixes for getting serdes onto the new fifo system. Compiles, at least Implement Eth flow control using pause frames parameterized fifo sizes, some reformatting remove unused old style fifo allow control of whether or not to honor flow control, adds some debug lines debug the rx side no longer used, replaced by newfifo version remove special last_line adjustment from ethernet port Firmware now inserts mac source address value in each frame. ...
Diffstat (limited to 'eth/rtl/verilog/header.vh')
-rw-r--r--eth/rtl/verilog/header.vh7
1 files changed, 0 insertions, 7 deletions
diff --git a/eth/rtl/verilog/header.vh b/eth/rtl/verilog/header.vh
deleted file mode 100644
index ca0b580e4..000000000
--- a/eth/rtl/verilog/header.vh
+++ /dev/null
@@ -1,7 +0,0 @@
-`define MAC_SOURCE_REPLACE_EN 1
-`define MAC_TARGET_CHECK_EN 1
-`define MAC_BROADCAST_FILTER_EN 1
-`define MAC_TX_FF_DEPTH 9
-`define MAC_RX_FF_DEPTH 9
-`define MAC_TARGET_XILINX 1
-// `define MAC_TARGET_ALTERA 1