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| author | jcorgan <jcorgan@221aa14e-8319-0410-a670-987f0aec2ac5> | 2008-09-08 01:00:12 +0000 |
|---|---|---|
| committer | jcorgan <jcorgan@221aa14e-8319-0410-a670-987f0aec2ac5> | 2008-09-08 01:00:12 +0000 |
| commit | 61f2f0214c5999ea42a368a4fc99f03d8eb28d1e (patch) | |
| tree | e7e24a9adc05ff1422fe3ada9926a51634741b47 /eth/rtl/verilog/flow_ctrl_tx.v | |
| download | uhd-61f2f0214c5999ea42a368a4fc99f03d8eb28d1e.tar.gz uhd-61f2f0214c5999ea42a368a4fc99f03d8eb28d1e.tar.bz2 uhd-61f2f0214c5999ea42a368a4fc99f03d8eb28d1e.zip | |
Merged r9433:9527 from features/gr-usrp2 into trunk. Adds usrp2 and gr-usrp2 top-level components. Trunk passes distcheck with mb-gcc installed, but currently not without them. The key issue is that when mb-gcc is not installed, the build system skips over the usrp2/firmware directory, and the firmware include files don't get put into the dist tarball. But we can't do the usual DIST_SUBDIRS method as the firmware is a subpackage.
git-svn-id: http://gnuradio.org/svn/gnuradio/trunk@9528 221aa14e-8319-0410-a670-987f0aec2ac5
Diffstat (limited to 'eth/rtl/verilog/flow_ctrl_tx.v')
| -rw-r--r-- | eth/rtl/verilog/flow_ctrl_tx.v | 36 |
1 files changed, 36 insertions, 0 deletions
diff --git a/eth/rtl/verilog/flow_ctrl_tx.v b/eth/rtl/verilog/flow_ctrl_tx.v new file mode 100644 index 000000000..9f7556de4 --- /dev/null +++ b/eth/rtl/verilog/flow_ctrl_tx.v @@ -0,0 +1,36 @@ +
+// TX side of flow control -- when other side sends PAUSE, we wait
+
+module flow_ctrl_tx
+ (input rst,
+ input tx_clk,
+ //host processor
+ input tx_pause_en,
+ // From MAC_rx_ctrl
+ input [15:0] pause_quanta,
+ input pause_quanta_val,
+ // MAC_tx_ctrl
+ output pause_apply,
+ input pause_quanta_sub);
+
+ // ******************************************************************************
+ // Inhibit our TX from transmitting because they sent us a PAUSE frame
+ // ******************************************************************************
+
+ reg [15:0] pause_quanta_counter;
+ reg pqval_d1, pqval_d2;
+
+ always @(posedge tx_clk) pqval_d1 <= pause_quanta_val;
+ always @(posedge tx_clk) pqval_d2 <= pqval_d1;
+
+ always @ (posedge tx_clk or posedge rst)
+ if (rst)
+ pause_quanta_counter <= 0;
+ else if (pqval_d1 & ~pqval_d2)
+ pause_quanta_counter <= pause_quanta;
+ else if((pause_quanta_counter!=0) & pause_quanta_sub)
+ pause_quanta_counter <= pause_quanta_counter - 1;
+
+ assign pause_apply = tx_pause_en & (pause_quanta_counter != 0);
+
+endmodule // flow_ctrl
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