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author | jcorgan <jcorgan@221aa14e-8319-0410-a670-987f0aec2ac5> | 2008-09-08 01:00:12 +0000 |
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committer | jcorgan <jcorgan@221aa14e-8319-0410-a670-987f0aec2ac5> | 2008-09-08 01:00:12 +0000 |
commit | 61f2f0214c5999ea42a368a4fc99f03d8eb28d1e (patch) | |
tree | e7e24a9adc05ff1422fe3ada9926a51634741b47 /eth/mac_rxfifo_int.v | |
download | uhd-61f2f0214c5999ea42a368a4fc99f03d8eb28d1e.tar.gz uhd-61f2f0214c5999ea42a368a4fc99f03d8eb28d1e.tar.bz2 uhd-61f2f0214c5999ea42a368a4fc99f03d8eb28d1e.zip |
Merged r9433:9527 from features/gr-usrp2 into trunk. Adds usrp2 and gr-usrp2 top-level components. Trunk passes distcheck with mb-gcc installed, but currently not without them. The key issue is that when mb-gcc is not installed, the build system skips over the usrp2/firmware directory, and the firmware include files don't get put into the dist tarball. But we can't do the usual DIST_SUBDIRS method as the firmware is a subpackage.
git-svn-id: http://gnuradio.org/svn/gnuradio/trunk@9528 221aa14e-8319-0410-a670-987f0aec2ac5
Diffstat (limited to 'eth/mac_rxfifo_int.v')
-rw-r--r-- | eth/mac_rxfifo_int.v | 80 |
1 files changed, 80 insertions, 0 deletions
diff --git a/eth/mac_rxfifo_int.v b/eth/mac_rxfifo_int.v new file mode 100644 index 000000000..9393cbd12 --- /dev/null +++ b/eth/mac_rxfifo_int.v @@ -0,0 +1,80 @@ + +module mac_rxfifo_int + (input clk, input rst, + + input Rx_mac_empty, + output Rx_mac_rd, + input [31:0] Rx_mac_data, + input [1:0] Rx_mac_BE, + input Rx_mac_sop, + input Rx_mac_eop, + input Rx_mac_err, + + output [31:0] wr_dat_o, + output wr_write_o, + output wr_done_o, + output wr_error_o, + input wr_ready_i, + input wr_full_i, + + // FIFO Status + output [15:0] fifo_occupied, + output fifo_full, + output fifo_empty + ); + + // Write side of short FIFO + // Inputs: full, Rx_mac_empty, Rx_mac_sop, Rx_mac_eop, Rx_mac_err, Rx_mac_data/BE + // Controls: write, datain, Rx_mac_rd + + wire write, full, read, empty, sop_o, eop_o, error_o; + + // Write side of short FIFO + assign write = ~full & ~Rx_mac_empty; + assign Rx_mac_rd = write; + + shortfifo #(.WIDTH(35)) mac_rx_sfifo + (.clk(clk),.rst(rst),.clear(0), + .datain({Rx_mac_sop,Rx_mac_eop,Rx_mac_err,Rx_mac_data}),.write(write),.full(full), + .dataout({sop_o,eop_o,error_o,wr_dat_o}),.read(read),.empty(empty), + .space(), .occupied(fifo_occupied[4:0]) ); + assign fifo_occupied[15:5] = 0; + assign fifo_full = full; + assign fifo_empty = empty; + + // Read side of short FIFO + // Inputs: empty, dataout, wr_ready_i, wr_full_i + // Controls: read, wr_dat_o, wr_write_o, wr_done_o, wr_error_o + + reg [1:0] rd_state; + localparam RD_IDLE = 0; + localparam RD_HAVEPKT = 1; + localparam RD_XFER = 2; + localparam RD_ERROR = 3; + + always @(posedge clk) + if(rst) + rd_state <= RD_IDLE; + else + case(rd_state) + RD_IDLE : + if(sop_o & ~empty) + rd_state <= RD_HAVEPKT; + RD_HAVEPKT : + if(wr_ready_i) + rd_state <= RD_XFER; + RD_XFER : + if(eop_o & ~empty) + rd_state <= RD_IDLE; + else if(wr_full_i) + rd_state <= RD_HAVEPKT; + RD_ERROR : + rd_state <= RD_IDLE; + endcase // case(rd_state) + + assign read = ~empty & ((rd_state == RD_XFER) | ((rd_state==RD_IDLE)&~sop_o)); + assign wr_write_o = ~empty & (rd_state == RD_XFER); + assign wr_done_o = ~empty & (rd_state == RD_XFER) & eop_o; + assign wr_error_o = ~empty & (rd_state == RD_XFER) & error_o; + +endmodule // mac_rxfifo_int |