diff options
| author | Johnathan Corgan <jcorgan@corganenterprises.com> | 2009-10-01 11:00:25 -0700 |
|---|---|---|
| committer | Johnathan Corgan <jcorgan@corganenterprises.com> | 2009-10-01 11:07:59 -0700 |
| commit | 1ff74777e47f3a2edefc5154484f2bdcb86c1a13 (patch) | |
| tree | 04f94ef4f7f06a210f7532592829332c7f2621f0 /eth/bench/verilog | |
| parent | 7b8f65256b5ea300187ebb6a359df2fa707a295d (diff) | |
| parent | 42fc55415af499980901c7787f44c7e74b4a9ce1 (diff) | |
| download | uhd-1ff74777e47f3a2edefc5154484f2bdcb86c1a13.tar.gz uhd-1ff74777e47f3a2edefc5154484f2bdcb86c1a13.tar.bz2 uhd-1ff74777e47f3a2edefc5154484f2bdcb86c1a13.zip | |
Merge branch 'new_eth' of http://gnuradio.org/git/matt into master
* 'new_eth' of http://gnuradio.org/git/matt: (42 commits)
Fix warnings, mostly from implicitly defined wires or unspecified widths
fullchip sim now compiles again, after moving eth and models over to new simple_gemac
remove unused opencores
remove debugging code
no idea where this came from, it shouldn't be here
Copied wb_1master back from quad radio
Remove old mac. Good riddance.
remove unused port
More xilinx fifos, more clean up of our fifos
might as well use a cascade fifo to help timing and give a little more capacity
fix a typo which caused tx glitches
Untested fixes for getting serdes onto the new fifo system. Compiles, at least
Implement Eth flow control using pause frames
parameterized fifo sizes, some reformatting
remove unused old style fifo
allow control of whether or not to honor flow control, adds some debug lines
debug the rx side
no longer used, replaced by newfifo version
remove special last_line adjustment from ethernet port
Firmware now inserts mac source address value in each frame.
...
Diffstat (limited to 'eth/bench/verilog')
| -rw-r--r-- | eth/bench/verilog/.gitignore | 4 | ||||
| -rw-r--r-- | eth/bench/verilog/100m.scr | 38 | ||||
| -rw-r--r-- | eth/bench/verilog/Phy_sim.v | 113 | ||||
| -rw-r--r-- | eth/bench/verilog/User_int_sim.v | 230 | ||||
| -rw-r--r-- | eth/bench/verilog/error.scr | 146 | ||||
| -rw-r--r-- | eth/bench/verilog/files.lst | 42 | ||||
| -rw-r--r-- | eth/bench/verilog/host_sim.v | 82 | ||||
| -rw-r--r-- | eth/bench/verilog/icomp.bat | 1 | ||||
| -rw-r--r-- | eth/bench/verilog/isim.bat | 1 | ||||
| -rw-r--r-- | eth/bench/verilog/jumbo_err.scr | 40 | ||||
| -rw-r--r-- | eth/bench/verilog/jumbos.scr | 27 | ||||
| -rw-r--r-- | eth/bench/verilog/mdio.scr | 52 | ||||
| -rw-r--r-- | eth/bench/verilog/miim_model.v | 14 | ||||
| -rw-r--r-- | eth/bench/verilog/misc.scr | 92 | ||||
| -rw-r--r-- | eth/bench/verilog/pause.scr | 45 | ||||
| -rw-r--r-- | eth/bench/verilog/tb_top.v | 1057 | ||||
| -rw-r--r-- | eth/bench/verilog/test.scr | 23 | ||||
| -rw-r--r-- | eth/bench/verilog/txmac.scr | 93 | ||||
| -rw-r--r-- | eth/bench/verilog/xlnx_glbl.v | 29 |
19 files changed, 0 insertions, 2129 deletions
diff --git a/eth/bench/verilog/.gitignore b/eth/bench/verilog/.gitignore deleted file mode 100644 index 86fc44f92..000000000 --- a/eth/bench/verilog/.gitignore +++ /dev/null @@ -1,4 +0,0 @@ -/a.out -/*.vcd -/*.sav -/*.lxt diff --git a/eth/bench/verilog/100m.scr b/eth/bench/verilog/100m.scr deleted file mode 100644 index 0dd59b894..000000000 --- a/eth/bench/verilog/100m.scr +++ /dev/null @@ -1,38 +0,0 @@ -// This tests just runs a few packets at 10/100 Mbps and 1 Gbps instead of only the usual 1 Gbps
-
-// Read from register 24 to confirm that Rx CRC check is enabled
-03 00 18 00 01 ff ff
-
-// Set speed to 1000 Mbps for a starter
-01 00 22 00 04
-
-// Setup Tx and Rx MAC addresses and type field to "IP"
-// Set Tx Data at offset 0, length 14 to 123456789ABC CBA987654321 0800
-10 00 00 00 0E 12 34 56 78 9A BC CB A9 87 65 43 21 08 00
-
-// Transmit a 1000-byte frame 1 time - and expect it to be received again!
-20 03 E8 00 01
-
-// Wait (indefinitely) for missing Rx packets
-22 00 00
-
-// Set speed to 100 Mbps - this is 10x slower!
-01 00 22 00 02
-
-// Transmit a 1000-byte frame 1 time - and expect it to be received again!
-20 03 E8 00 01
-
-// Wait (indefinitely) for missing Rx packets
-22 00 00
-
-// Set speed to 10 Mbps - this is yet another 10x slower!
-01 00 22 00 01
-
-// Transmit a 1000-byte frame 1 time - and expect it to be received again!
-20 03 E8 00 01
-
-// Wait (indefinitely) for missing Rx packets
-22 00 00
-
-// Halt
-FF
diff --git a/eth/bench/verilog/Phy_sim.v b/eth/bench/verilog/Phy_sim.v deleted file mode 100644 index f51ddbd82..000000000 --- a/eth/bench/verilog/Phy_sim.v +++ /dev/null @@ -1,113 +0,0 @@ -//////////////////////////////////////////////////////////////////////
-//// ////
-//// Phy_sim.v ////
-//// ////
-//// This file is part of the Ethernet IP core project ////
-//// http://www.opencores.org/projects.cgi/web/ethernet_tri_mode/////
-//// ////
-//// Author(s): ////
-//// - Jon Gao (gaojon@yahoo.com) ////
-//// ////
-//// ////
-//////////////////////////////////////////////////////////////////////
-//// ////
-//// Copyright (C) 2001 Authors ////
-//// ////
-//// This source file may be used and distributed without ////
-//// restriction provided that this copyright statement is not ////
-//// removed from the file and that any derivative work contains ////
-//// the original copyright notice and the associated disclaimer. ////
-//// ////
-//// This source file is free software; you can redistribute it ////
-//// and/or modify it under the terms of the GNU Lesser General ////
-//// Public License as published by the Free Software Foundation; ////
-//// either version 2.1 of the License, or (at your option) any ////
-//// later version. ////
-//// ////
-//// This source is distributed in the hope that it will be ////
-//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
-//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
-//// PURPOSE. See the GNU Lesser General Public License for more ////
-//// details. ////
-//// ////
-//// You should have received a copy of the GNU Lesser General ////
-//// Public License along with this source; if not, download it ////
-//// from http://www.opencores.org/lgpl.shtml ////
-//// ////
-//////////////////////////////////////////////////////////////////////
-//
-// CVS Revision History
-//
-// $Log: Phy_sim.v,v $
-// Revision 1.3 2006/11/17 17:53:07 maverickist
-// no message
-//
-// Revision 1.2 2006/01/19 14:07:50 maverickist
-// verification is complete.
-//
-// Revision 1.1.1.1 2005/12/13 01:51:44 Administrator
-// no message
-//
-
-`timescale 1ns/100ps
-
-module Phy_sim(
- input Gtx_clk, // Used only in GMII mode
- output Rx_clk,
- output Tx_clk, // Used only in MII mode
- input Tx_er,
- input Tx_en,
- input [7:0] Txd,
- output Rx_er,
- output Rx_dv,
- output [7:0] Rxd,
- output Crs,
- output Col,
- input [2:0] Speed,
- input Done
-);
-
-//////////////////////////////////////////////////////////////////////
-// this file used to simulate Phy.
-// generate clk and loop the Tx data to Rx data
-// full duplex mode can be verified on loop mode.
-//////////////////////////////////////////////////////////////////////
-//////////////////////////////////////////////////////////////////////
-// internal signals
-//////////////////////////////////////////////////////////////////////
-reg Clk_25m; // Used for 100 Mbps mode
-reg Clk_2_5m; // Used for 10 Mbps mode
-
-//wire Rx_clk;
-//wire Tx_clk; // Used only in MII mode
-
- initial
- begin
- #10;
- while ( !Done )
- begin
- #20 Clk_25m = 0;
- #20 Clk_25m = 1;
- end
- end
-
- initial
- begin
- #10;
- while ( !Done )
- begin
- #200 Clk_2_5m = 0;
- #200 Clk_2_5m = 1;
- end
- end
-
- assign Rx_clk = Speed[2] ? Gtx_clk : Speed[1] ? Clk_25m : Speed[0] ? Clk_2_5m : 0;
- assign Tx_clk = Speed[2] ? Gtx_clk : Speed[1] ? Clk_25m : Speed[0] ? Clk_2_5m : 0;
-
- assign Rx_dv = Tx_en;
- assign Rxd = Txd;
- assign Rx_er = Tx_er;
- assign Crs = Tx_en;
- assign Col = 0;
-
-endmodule
diff --git a/eth/bench/verilog/User_int_sim.v b/eth/bench/verilog/User_int_sim.v deleted file mode 100644 index 3f4aa249b..000000000 --- a/eth/bench/verilog/User_int_sim.v +++ /dev/null @@ -1,230 +0,0 @@ -//////////////////////////////////////////////////////////////////////
-//// ////
-//// User_input_sim.v ////
-//// ////
-//// This file is part of the Ethernet IP core project ////
-//// http://www.opencores.org/projects.cgi/web/ethernet_tri_mode/////
-//// ////
-//// Author(s): ////
-//// - Jon Gao (gaojon@yahoo.com) ////
-//// ////
-//// ////
-//////////////////////////////////////////////////////////////////////
-//// ////
-//// Copyright (C) 2001 Authors ////
-//// ////
-//// This source file may be used and distributed without ////
-//// restriction provided that this copyright statement is not ////
-//// removed from the file and that any derivative work contains ////
-//// the original copyright notice and the associated disclaimer. ////
-//// ////
-//// This source file is free software; you can redistribute it ////
-//// and/or modify it under the terms of the GNU Lesser General ////
-//// Public License as published by the Free Software Foundation; ////
-//// either version 2.1 of the License, or (at your option) any ////
-//// later version. ////
-//// ////
-//// This source is distributed in the hope that it will be ////
-//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
-//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
-//// PURPOSE. See the GNU Lesser General Public License for more ////
-//// details. ////
-//// ////
-//// You should have received a copy of the GNU Lesser General ////
-//// Public License along with this source; if not, download it ////
-//// from http://www.opencores.org/lgpl.shtml ////
-//// ////
-//////////////////////////////////////////////////////////////////////
-//
-// CVS Revision History
-//
-// $Log: User_int_sim.v,v $
-// Revision 1.3 2006/11/17 17:53:07 maverickist
-// no message
-//
-// Revision 1.2 2006/01/19 14:07:50 maverickist
-// verification is complete.
-//
-// Revision 1.2 2005/12/13 12:15:35 Administrator
-// no message
-//
-// Revision 1.1.1.1 2005/12/13 01:51:44 Administrator
-// no message
-//
-module User_int_sim (
- Reset,
- Clk_user,
- CPU_init_end,
-
- Rx_mac_ra,
- Rx_mac_rd,
- Rx_mac_data,
- Rx_mac_BE,
- Rx_mac_pa,
- Rx_mac_sop,
- Rx_mac_eop,
-
- Tx_mac_wa,
- Tx_mac_wr,
- Tx_mac_data,
- Tx_mac_BE,
- Tx_mac_sop,
- Tx_mac_eop
-);
-
- input Reset;
- input Clk_user;
- input CPU_init_end;
-
- input Rx_mac_ra;
- output Rx_mac_rd;
- input [31:0] Rx_mac_data;
- input [1:0] Rx_mac_BE;
- input Rx_mac_pa;
- input Rx_mac_sop;
- input Rx_mac_eop;
-
- input Tx_mac_wa;
- output reg Tx_mac_wr;
- output reg [31:0] Tx_mac_data;
- output reg [1:0] Tx_mac_BE; // Big endian
- output reg Tx_mac_sop;
- output reg Tx_mac_eop;
-
-//////////////////////////////////////////////////////////////////////
-// Internal signals
-//////////////////////////////////////////////////////////////////////
-
- reg [4:0] operation;
- reg [31:0] data;
- reg Rx_mac_rd;
- reg Start_tran;
-
-//////////////////////////////////////////////////////////////////////
-//generate Tx user data
-//////////////////////////////////////////////////////////////////////
-
- initial
- begin
- operation = 0;
- data = 0;
- end
-
- task SendPacket;
- input [15:0] Length;
- input [7:0] StartByte;
-
- reg [15:0] Counter;
- reg [7:0] TxData;
-
- begin
- Counter=Length;
- TxData = StartByte;
- Tx_mac_sop = 1; // First time
- while ( Counter>0 )
- begin
- while ( !Tx_mac_wa )
- begin
- Tx_mac_wr = 0;
- @( posedge Clk_user );
- end
-
- Tx_mac_data[31:24] = TxData;
- Tx_mac_data[23:16] = TxData+1;
- Tx_mac_data[15:8] = TxData+2;
- Tx_mac_data[ 7:0] = TxData+3;
- TxData = TxData+4;
- if ( Counter<=4 )
- begin
- // Indicate how many bytes are valid
- if ( Counter==4 )
- Tx_mac_BE = 2'b00;
- else
- Tx_mac_BE = Counter;
- Tx_mac_eop = 1;
- end
- Tx_mac_wr = 1;
-
- if ( Counter >= 4 )
- Counter = Counter - 4;
- else
- Counter = 0;
- @( posedge Clk_user );
- Tx_mac_sop = 0;
- end
-
- Tx_mac_eop = 0;
- Tx_mac_wr = 0;
- Tx_mac_data = 32'h0;
- Tx_mac_BE = 2'b00;
- end
- endtask
-
- always @( posedge Clk_user or posedge Reset )
- if (Reset)
- Start_tran <= 0;
- else if (Tx_mac_eop && !Tx_mac_wa)
- Start_tran <= 0;
- else if (Tx_mac_wa)
- Start_tran <= 1;
-
- always @(posedge Clk_user)
- if (Tx_mac_wa && CPU_init_end)
- /* $ip_32W_gen("../data/config.ini",operation,data); */
- ;
- else
- begin
- operation <= 0;
- data <= 0;
- end
-
- initial
- begin
- Tx_mac_sop = 0;
- Tx_mac_eop = 0;
- Tx_mac_wr = 0;
- Tx_mac_data = 32'h0;
- Tx_mac_BE = 2'b00;
-
- #100;
- while ( Reset )
- @( posedge Clk_user );
-
- @( posedge Clk_user );
-
- while ( !CPU_init_end )
- @( posedge Clk_user );
-
- SendPacket( 64, 8'h11 );
- repeat( 20 )
- @( posedge Clk_user );
- SendPacket( 1500, 8'h12 );
-
- end
-
-// assign Tx_mac_data = data;
-// assign Tx_mac_wr = operation[4];
-// assign Tx_mac_sop = operation[3];
-// assign Tx_mac_eop = operation[2];
-// assign Tx_mac_BE = operation[1:0];
-
-//////////////////////////////////////////////////////////////////////
-//verify Rx user data
-//////////////////////////////////////////////////////////////////////
-
- always @ (posedge Clk_user or posedge Reset)
- if (Reset)
- Rx_mac_rd <= 0;
- else if (Rx_mac_ra)
- Rx_mac_rd <= 1;
- else
- Rx_mac_rd <= 0;
-
- always @ (posedge Clk_user )
- if (Rx_mac_pa)
- /* $ip_32W_check( Rx_mac_data,
- {Rx_mac_sop,Rx_mac_eop,Rx_mac_eop?Rx_mac_BE:2'b0});
- */
- ;
-
-endmodule
diff --git a/eth/bench/verilog/error.scr b/eth/bench/verilog/error.scr deleted file mode 100644 index af42634a8..000000000 --- a/eth/bench/verilog/error.scr +++ /dev/null @@ -1,146 +0,0 @@ -// This tests sends 5 packets, injecting a bit error in two of them
-// to verify the Rx CRC check works. The corresponding RMON statistics
-// counter is finally checked to verify that the error was registered
-
-// Read from register 24 to confirm that Rx CRC check is enabled
-03 00 18 00 01 ff ff
-
-// Set speed to 1000 Mbps
-01 00 22 00 04
-
-// Setup Tx and Rx MAC addresses and type field to "IP"
-// Set Tx Data at offset 0, length 14 to 123456789ABC CBA987654321 0800
-10 00 00 00 0E 12 34 56 78 9A BC CB A9 87 65 43 21 08 00
-
-//--- Packets #0 & 1 --------------------------------------------------------
-
-// Transmit a 200-byte frame 1 time - and expect it to be received again!
-20 00 C8 00 01
-
-// Wait (indefinitely) for missing Rx packets
-22 00 00
-
-// Transmit a 200-byte frame 1 time - but expect to receive it with error!
-25 00 C8 00 01
-
-// Inject a single bit error in the packet (data bit 0) - this will cause a CRC error
-23 00 01
-
-// Wait (indefinitely) for missing Rx packets
-22 00 00
-
-//--- Packets #2 & 3 --------------------------------------------------------
-
-// Transmit a 200-byte frame 1 time - and expect it to be received again!
-20 00 C8 00 01
-
-// Wait (indefinitely) for missing Rx packets
-22 00 00
-
-// Transmit a 200-byte frame 1 time - but expect to receive it with error!
-25 00 C8 00 01
-
-// Inject a single bit error in the packet (data bit 7) - this will cause a CRC error
-23 00 80
-
-// Wait (indefinitely) for missing Rx packets
-22 00 00
-
-//--- Packets #4 & 5 --------------------------------------------------------
-
-// Transmit a 200-byte frame 1 time - and expect it to be received again!
-20 00 C8 00 01
-
-// Wait (indefinitely) for missing Rx packets
-22 00 00
-
-// Transmit a 200-byte frame 1 time - but don't expect it to be received again!
-21 00 C8 00 01
-
-// Inject a single bit error in the packet (RxEn) - this will cause a packet discard!
-// (because it happens early in the packet)
-23 01 00
-
-// Wait (indefinitely) for missing Rx packets
-22 00 00
-
-//--- Packets #6 & 7 --------------------------------------------------------
-
-// Transmit a 200-byte frame 1 time - and expect it to be received again!
-20 00 C8 00 01
-
-// Wait (indefinitely) for missing Rx packets
-22 00 00
-
-// Transmit a 200-byte frame 1 time - but don't expect it to be received again!
-21 00 C8 00 01
-
-// Inject a single bit error in the packet (RxEr)
-23 02 00
-
-// Wait (indefinitely) for missing Rx packets
-22 00 00
-
-//--- Packet #8 -------------------------------------------------------------
-
-// Transmit a 200-byte frame 1 time - and expect it to be received again!
-20 00 C8 00 01
-
-// Wait (indefinitely) for missing Rx packets
-22 00 00
-
-//---------------------------------------------------------------------------
-
-// Set CPU_rd_addr to address RxCRCErrCounter
-01 00 1C 00 05
-
-// Assert CPU_rd_apply
-01 00 1D 00 01
-
-// Kill a little time while waiting for CPU_rd_grant to assert...
-02 00 1E
-02 00 1E
-02 00 1E
-02 00 1E
-
-// Confirm that CPU_rd_grant is asserted
-03 00 1E 00 01 ff ff
-
-// Read & check low part of RxCRCErrCounter (0x0002)
-03 00 1F 00 02 ff ff
-
-// Read & check high part of RxCRCErrCounter (0x0000)
-03 00 20 00 00 ff ff
-
-// Negate CPU_rd_apply
-01 00 1D 00 00
-
-//---------------------------------------------------------------------------
-
-// Set CPU_rd_addr to address RxTooShortTooLongCounter
-01 00 1C 00 07
-
-// Assert CPU_rd_apply
-01 00 1D 00 01
-
-// Kill a little time while waiting for CPU_rd_grant to assert...
-02 00 1E
-02 00 1E
-02 00 1E
-02 00 1E
-
-// Confirm that CPU_rd_grant is asserted
-03 00 1E 00 01 ff ff
-
-// Read & check low part of RxTooShortTooLongCounter (0x0002)
-03 00 1F 00 02 ff ff
-
-// Read & check high part of RxTooShortTooLongCounter (0x0000)
-03 00 20 00 00 ff ff
-
-// Negate CPU_rd_apply
-01 00 1D 00 00
-
-
-// Halt
-FF
diff --git a/eth/bench/verilog/files.lst b/eth/bench/verilog/files.lst deleted file mode 100644 index 6175a4d43..000000000 --- a/eth/bench/verilog/files.lst +++ /dev/null @@ -1,42 +0,0 @@ -../../rtl/verilog/MAC_rx/Broadcast_filter.v
-../../rtl/verilog/MAC_rx/CRC_chk.v
-../../rtl/verilog/MAC_rx/MAC_rx_add_chk.v
-../../rtl/verilog/MAC_rx/MAC_rx_ctrl.v
-../../rtl/verilog/MAC_rx/MAC_rx_FF.v
-
-../../rtl/verilog/MAC_tx/CRC_gen.v
-../../rtl/verilog/MAC_tx/flow_ctrl.v
-../../rtl/verilog/MAC_tx/MAC_tx_addr_add.v
-../../rtl/verilog/MAC_tx/MAC_tx_ctrl.v
-../../rtl/verilog/MAC_tx/MAC_tx_FF.v
-../../rtl/verilog/MAC_tx/Ramdon_gen.v
-
-../../rtl/verilog/miim/eth_clockgen.v
-../../rtl/verilog/miim/eth_outputcontrol.v
-../../rtl/verilog/miim/eth_shiftreg.v
-
-../../rtl/verilog/RMON/RMON_addr_gen.v
-../../rtl/verilog/RMON/RMON_ctrl.v
-../../rtl/verilog/RMON/RMON_dpram.v
-
-../../rtl/verilog/TECH/duram.v
-../../rtl/verilog/TECH/eth_clk_div2.v
-../../rtl/verilog/TECH/eth_clk_switch.v
-
-../../rtl/verilog/TECH/xilinx/BUFGMUX.v
-../../rtl/verilog/TECH/xilinx/RAMB16_S36_S36.v
-
-../../rtl/verilog/Clk_ctrl.v
-../../rtl/verilog/eth_miim.v
-../../rtl/verilog/MAC_rx.v
-../../rtl/verilog/MAC_top.v
-../../rtl/verilog/MAC_tx.v
-../../rtl/verilog/Phy_int.v
-../../rtl/verilog/Reg_int.v
-../../rtl/verilog/RMON.v
-
-../../bench/verilog/Phy_sim.v
-../../bench/verilog/User_int_sim.v
-../../bench/verilog/host_sim.v
-../../bench/verilog/xlnx_glbl.v
-../../bench/verilog/tb_top.v
diff --git a/eth/bench/verilog/host_sim.v b/eth/bench/verilog/host_sim.v deleted file mode 100644 index 55abb8508..000000000 --- a/eth/bench/verilog/host_sim.v +++ /dev/null @@ -1,82 +0,0 @@ -module host_sim(
- input Reset,
- input Clk_reg,
- output reg CSB,
- output reg WRB,
- output reg CPU_init_end,
- output reg [15:0] CD_in,
- input [15:0] CD_out,
- output reg [7:0] CA
-);
-
-////////////////////////////////////////
-
-task CPU_init;
- begin
- CA = 0;
- CD_in = 0;
- WRB = 1;
- CSB = 1;
- end
-endtask
-
-////////////////////////////////////////
-
-task CPU_wr;
- input [6:0] Addr;
- input [15:0] Data;
- begin
- CA = {Addr,1'b0};
- CD_in = Data;
- WRB = 0;
- CSB = 0;
- #20;
- CA = 0;
- CD_in = 0;
- WRB = 1;
- CSB = 1;
- #20;
- end
-endtask
-
-/////////////////////////////////////////
-
-task CPU_rd;
- input [6:0] Addr;
- begin
- CA = {Addr,1'b0};
- WRB = 1;
- CSB = 0;
- #20;
- CA = 0;
- WRB = 1;
- CSB = 1;
- #20;
- end
-endtask
-
-/////////////////////////////////////////
-
-integer i;
-
-reg [31:0] CPU_data [255:0];
-reg [7:0] write_times;
-reg [7:0] write_add;
-reg [15:0] write_data;
-
-initial
- begin
- CPU_init;
- CPU_init_end=0;
- //$readmemh("../data/CPU.vec",CPU_data);
- //{write_times,write_add,write_data}=CPU_data[0];
- {write_times,write_add,write_data}='b0;
- #90;
- for (i=0;i<write_times;i=i+1)
- begin
- {write_times,write_add,write_data}=CPU_data[i];
- CPU_wr(write_add[6:0],write_data);
- end
- CPU_init_end=1;
- end
-endmodule
diff --git a/eth/bench/verilog/icomp.bat b/eth/bench/verilog/icomp.bat deleted file mode 100644 index 11e221e08..000000000 --- a/eth/bench/verilog/icomp.bat +++ /dev/null @@ -1 +0,0 @@ -iverilog -I ..\..\rtl\verilog -c files.lst
diff --git a/eth/bench/verilog/isim.bat b/eth/bench/verilog/isim.bat deleted file mode 100644 index e77969659..000000000 --- a/eth/bench/verilog/isim.bat +++ /dev/null @@ -1 +0,0 @@ -vvp a.out %*
diff --git a/eth/bench/verilog/jumbo_err.scr b/eth/bench/verilog/jumbo_err.scr deleted file mode 100644 index b0177f474..000000000 --- a/eth/bench/verilog/jumbo_err.scr +++ /dev/null @@ -1,40 +0,0 @@ -// This test performs transmission & reception of several Jumbo-frame of ~2Kbytes
-// In one of the frames an error is injected to allow analysis of how the
-// MAC Rx interface reacts to errors in long packets
-
-// Read from register 24 to confirm that Rx CRC check is enabled
-03 00 18 00 01 ff ff
-
-// Set speed to 1000 Mbps
-01 00 22 00 04
-
-// Setup Tx and Rx MAC addresses and type field to "IP"
-// Set Tx Data at offset 0, length 14 to 123456789ABC CBA987654321 0800
-10 00 00 00 0E 12 34 56 78 9A BC CB A9 87 65 43 21 08 00
-
-// Transmit a 2049-byte frame 2 times - and expect them to be received again!
-20 08 02 00 02
-
-// Wait (indefinitely) for missing Rx packets
-22 00 00
-
-// Transmit a 2049-byte frame 1 time - but expect to receive it with error!
-25 08 02 00 01
-
-// Delay 256 NOPs to time the error injection to be late in the packet
-0F 01 00
-
-// Inject a single bit error in the packet (data bit 0)
-23 01 00
-
-// Wait (indefinitely) for missing Rx packets
-22 00 00
-
-// Transmit a 2049-byte frame 2 times - and expect them to be received again!
-20 08 01 00 02
-
-// Wait (indefinitely) for missing Rx packets
-22 00 00
-
-// Halt
-FF
diff --git a/eth/bench/verilog/jumbos.scr b/eth/bench/verilog/jumbos.scr deleted file mode 100644 index f48870bd5..000000000 --- a/eth/bench/verilog/jumbos.scr +++ /dev/null @@ -1,27 +0,0 @@ -// This test performs transmission & reception of several Jumbo-frames of ~2Kbytes each
-// At the same time it demonstrates the wire-speed capabilities of the core
-
-// Read from register 24 to confirm that Rx CRC check is enabled
-03 00 18 00 01 ff ff
-
-// Set speed to 1000 Mbps
-01 00 22 00 04
-
-// Setup Tx and Rx MAC addresses and type field to "IP"
-// Set Tx Data at offset 0, length 14 to 123456789ABC CBA987654321 0800
-10 00 00 00 0E 12 34 56 78 9A BC CB A9 87 65 43 21 08 00
-
-// Transmit a 2047-byte frame 3 times - and expect them to be received again!
-20 07 ff 00 03
-// Transmit a 2048-byte frame 3 times - and expect them to be received again!
-20 08 00 00 03
-// Transmit a 2049-byte frame 3 times - and expect them to be received again!
-20 08 01 00 03
-// Transmit a 2050-byte frame 3 times - and expect them to be received again!
-20 08 02 00 03
-
-// Wait (indefinitely) for missing Rx packets
-22 00 00
-
-// Halt
-FF
diff --git a/eth/bench/verilog/mdio.scr b/eth/bench/verilog/mdio.scr deleted file mode 100644 index 8ad9969b9..000000000 --- a/eth/bench/verilog/mdio.scr +++ /dev/null @@ -1,52 +0,0 @@ -// Read from register 24 to confirm that Rx CRC check is enabled
-03 00 18 00 01 ff ff
-
-// Set speed to 1000 Mbps
-01 00 22 00 04
-
-// Set MDIO clock (MDC) divider to 4 to speed up test
-01 00 23 00 04
-03 00 23 00 04 ff ff
-
-// Check default (reset) values in new (added) MDIO registers
-//03 00 23 00 64 ff ff
-03 00 24 00 00 ff ff
-03 00 25 00 00 ff ff
-03 00 26 00 00 ff ff
-03 00 27 00 00 ff ff
-03 00 28 00 00 ff ff
-
-// Set RGAD=0x00 (all zeroes), FIAD=0x1f (all ones), check it
-// - these values allows easy recognition in the waveform
-01 00 25 00 1f
-03 00 25 00 1f ff ff
-
-// Now start the read operation by writing a 1 to the MIICOMMAND[1] - RSTAT
-01 00 24 00 02
-03 00 24 00 02 ff ff
-
-// Delay for 768 NOP
-0F 03 00
-
-// Check that the read operation has completed
-03 00 28 00 00 ff ff
-
-// Set RGAD=0x1f (all ones), FIAD=0x00 (all zeroes), check it
-// - these values allows easy recognition in the waveform
-01 00 25 1f 00
-03 00 25 1f 00 ff ff
-// Set MIITX_DATA = 0xAAAA, check it
-01 00 26 AA AA
-03 00 26 AA AA ff ff
-// Check MIISTATUS - must still be zero
-03 00 28 00 00 ff ff
-
-// Now start the write operation by writing a 1 to the MIICOMMAND[2] - WCTRLDATA
-01 00 24 00 04
-03 00 24 00 04 ff ff
-
-// Delay for 768 NOP
-0F 03 00
-
-// Check that the write operation has completed
-03 00 28 00 00 ff ff
diff --git a/eth/bench/verilog/miim_model.v b/eth/bench/verilog/miim_model.v deleted file mode 100644 index 936d99a80..000000000 --- a/eth/bench/verilog/miim_model.v +++ /dev/null @@ -1,14 +0,0 @@ - -// Skeleton PHY interface simulator - -module miim_model(input mdc_i, - inout mdio, - input phy_resetn_i, - input phy_clk_i, - output phy_intn_o, - output [2:0] speed_o); - - assign phy_intn_o = 1; // No interrupts - assign speed_o = 3'b100; // 1G mode - -endmodule // miim_model diff --git a/eth/bench/verilog/misc.scr b/eth/bench/verilog/misc.scr deleted file mode 100644 index 092362964..000000000 --- a/eth/bench/verilog/misc.scr +++ /dev/null @@ -1,92 +0,0 @@ -// Read from register 24 to confirm that Rx CRC check is enabled
-03 00 18 00 01 ff ff
-
-// Set speed to 1000 Mbps
-01 00 22 00 04
-
-// Write MAC address 12 35 56 78 9A BC to Rx Address buffer
-01 00 10 00 00
-01 00 0f 00 12
-01 00 11 00 01
-01 00 11 00 00
-01 00 10 00 01
-01 00 0f 00 34
-01 00 11 00 01
-01 00 11 00 00
-01 00 10 00 02
-01 00 0f 00 56
-01 00 11 00 01
-01 00 11 00 00
-01 00 10 00 03
-01 00 0f 00 78
-01 00 11 00 01
-01 00 11 00 00
-01 00 10 00 04
-01 00 0f 00 9A
-01 00 11 00 01
-01 00 11 00 00
-01 00 10 00 05
-01 00 0f 00 BC
-01 00 11 00 01
-01 00 11 00 00
-
-// Write 1 to register 14, MAC_rx_add_chk_en
-// This turns on the Rx Destination MAC address filter
-01 00 0e 00 01
-
-// Setup Tx and Rx MAC addresses and type field to "IP"
-// Set Tx Data at offset 0, length 14 to 123456789ABC CBA987654321 0800
-// (i.e. Destination MAC address is 123456789ABC matching the above)
-10 00 00 00 0E 12 34 56 78 9A BC CB A9 87 65 43 21 08 00
-
-// Transmit a 60-byte frame 1 time - and expect it to be received again!
-20 00 3C 00 01
-// Transmit a 61-byte frame 1 time - and expect it to be received again!
-20 00 3D 00 01
-// Transmit a 62-byte frame 1 time - and expect it to be received again!
-20 00 3E 00 01
-// Transmit a 63-byte frame 1 time - and expect it to be received again!
-20 00 3F 00 01
-// Transmit a 64-byte frame 1 time - and expect it to be received again!
-20 00 40 00 01
-
-// Transmit a 500-byte frame 1 time - and expect it to be received again!
-20 01 4C 00 01
-
-// Transmit a 1500-byte frame 1 time - and expect it to be received again!
-20 05 DC 00 01
-
-// Transmit a 1514-byte frame 1 time - and expect it to be received again!
-20 05 EA 00 01
-
-// Transmit a 60-byte frame 3 times - and expect them to be received again!
-20 00 3C 00 03
-// Transmit a 61-byte frame 3 times - and expect them to be received again!
-20 00 3D 00 03
-// Transmit a 62-byte frame 3 times - and expect them to be received again!
-20 00 3E 00 03
-// Transmit a 63-byte frame 3 times - and expect them to be received again!
-20 00 3F 00 03
-// Transmit a 64-byte frame 3 times - and expect them to be received again!
-20 00 40 00 03
-
-// Transmit a 1510-byte frame 1 time - and expect it to be received again!
-20 05 E6 00 01
-
-// Wait (indefinitely) for missing Rx packets
-22 00 00
-
-// Change Tx MAC to something different - we won't receive frames with this ID
-10 00 00 00 06 11 22 33 44 55 66
-
-// Transmit a 60 byte frame 3 times - but don't expect them to be received!
-21 00 3C 00 03
-
-//// Change Tx MAC back to 12 34 56 78 9A BC
-10 00 00 00 06 12 34 56 78 9A BC
-
-// Transmit a 60 byte frame 3 times - and expect them to be received again!
-20 00 3C 00 03
-
-// Wait (indefinitely) for missing Rx packets
-22 00 00
diff --git a/eth/bench/verilog/pause.scr b/eth/bench/verilog/pause.scr deleted file mode 100644 index be74027e3..000000000 --- a/eth/bench/verilog/pause.scr +++ /dev/null @@ -1,45 +0,0 @@ -// This test demonstrates the ability to transmit a PAUSE frame, and the effect of
-// a PAUSE frame on the receiver
-
-// Read from register 24 to confirm that Rx CRC check is enabled
-03 00 18 00 01 ff ff
-
-// Set speed to 1000 Mbps
-01 00 22 00 04
-
-// Setup Tx and Rx MAC addresses and type field to "IP"
-// Set Tx Data at offset 0, length 14 to 123456789ABC CBA987654321 0800
-10 00 00 00 0E 12 34 56 78 9A BC CB A9 87 65 43 21 08 00
-
-// Set PAUSE quanta to 256 - corresponding to a pause of 256x512 = 128Kb = 16KB
-01 00 03 01 00
-
-// Enable the transmitter to send a PAUSE frame
-01 00 02 00 01
-
-// Enable the transmitter to react to received PAUSE frames
-01 00 0b 00 01
-
-// Expect to receive a PAUSE frame with quanta 256
-24 01 00
-
-// Transmit a 512-byte frame 1 time - and expect it to be received again!
-20 02 00 00 01
-
-// Request the transmission of a PAUSE frame - it will loopback to ourselves and delay
-// further transmission for a period of 16 KB, causing a significant (visible) delay
-// between first and second 512-byte frame!
-01 00 0c 00 01
-
-// - now this second time, we will experience a delay
-// Transmit a 512-byte frame 1 time - and expect it to be received again!
-20 02 00 00 01
-// - and a final 3rd time
-// Transmit a 512-byte frame 1 time - and expect it to be received again!
-20 02 00 00 01
-
-// Wait (indefinitely) for missing Rx packets
-22 00 00
-
-// Halt
-FF
diff --git a/eth/bench/verilog/tb_top.v b/eth/bench/verilog/tb_top.v deleted file mode 100644 index e54bc201b..000000000 --- a/eth/bench/verilog/tb_top.v +++ /dev/null @@ -1,1057 +0,0 @@ -`timescale 1 ns / 1 ps
-
-//////////////////////////////////////////////////////////////////////
-//// ////
-//// tb_top.v ////
-//// ////
-//// This file is part of the Ethernet IP core project ////
-//// http://www.opencores.org/projects.cgi/web/ethernet_tri_mode/////
-//// ////
-//// Author(s): ////
-//// - Jon Gao (gaojon@yahoo.com) ////
-//// ////
-//// ////
-//////////////////////////////////////////////////////////////////////
-//// ////
-//// Copyright (C) 2001 Authors ////
-//// ////
-//// This source file may be used and distributed without ////
-//// restriction provided that this copyright statement is not ////
-//// removed from the file and that any derivative work contains ////
-//// the original copyright notice and the associated disclaimer. ////
-//// ////
-//// This source file is free software; you can redistribute it ////
-//// and/or modify it under the terms of the GNU Lesser General ////
-//// Public License as published by the Free Software Foundation; ////
-//// either version 2.1 of the License, or (at your option) any ////
-//// later version. ////
-//// ////
-//// This source is distributed in the hope that it will be ////
-//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
-//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
-//// PURPOSE. See the GNU Lesser General Public License for more ////
-//// details. ////
-//// ////
-//// You should have received a copy of the GNU Lesser General ////
-//// Public License along with this source; if not, download it ////
-//// from http://www.opencores.org/lgpl.shtml ////
-//// ////
-//////////////////////////////////////////////////////////////////////
-//
-// CVS Revision History
-//
-// $Log: tb_top.v,v $
-// Revision 1.3 2006/01/19 14:07:51 maverickist
-// verification is complete.
-//
-// Revision 1.2 2005/12/16 06:44:13 Administrator
-// replaced tab with space.
-// passed 9.6k length frame test.
-//
-// Revision 1.1.1.1 2005/12/13 01:51:44 Administrator
-// no message
-//
-
-module tb_top;
-
- //-------------------- Instantiate Xilinx glbl module ----------------------
- // - this is needed to get ModelSim to work because e.g. I/O buffer models
- // refer directly to glbl.GTS and similar signals
-
- wire GSR;
- wire GTS;
- xlnx_glbl glbl( .GSR( GSR ), .GTS( GTS ) );
-
- reg VLOG_ExitSignal = 0;
- reg Done = 0;
- reg Error = 0;
-
- //-------------------------------------------------------------------------
-
- // System signals
- wire Reset;
- reg Clk_125M;
- reg Clk_user;
-
- reg RST_I;
- reg CLK_I;
- reg STB_I;
- reg CYC_I;
- reg [6:0] ADR_I;
- reg WE_I;
- reg [15:0] DAT_I;
- wire [15:0] DAT_O;
- wire ACK_O;
-
- // User interface (Rx)
- wire Rx_mac_ra;
- reg Rx_mac_rd = 0;
- wire [31:0] Rx_mac_data;
- wire [1:0] Rx_mac_BE;
- wire Rx_mac_pa;
- wire Rx_mac_sop;
- wire Rx_mac_err;
- wire Rx_mac_eop;
-
- // User interface (Tx)
- wire Tx_mac_wa;
- reg Tx_mac_wr = 0;
- reg [31:0] Tx_mac_data = 32'bx;
- reg [1:0] Tx_mac_BE = 2'bx;
- reg Tx_mac_sop = 1'bx;
- reg Tx_mac_eop = 1'bx;
-
- // PHY interface (GMII/MII)
- wire Gtx_clk;
- wire Rx_clk;
- wire Tx_clk;
- wire Tx_er;
- wire Tx_en;
- wire [7:0] Txd;
- wire Rx_er;
- wire Rx_dv;
- wire [7:0] Rxd;
- wire Crs;
- wire Col;
-
- // PHY int host interface
-
- wire Line_loop_en;
- wire [2:0] Speed;
-
- // MDIO interface
- wire Mdio; // MII Management Data In
- wire Mdc; // MII Management Data Clock
-
- //-------------------------------------------------------------------------
-
- // Generate generic reset signal from Wishbone specific one
- assign Reset = RST_I;
-
- MAC_top U_MAC_top(
- // System signals
- .Clk_125M ( Clk_125M ),
- .Clk_user ( Clk_user ),
- .Speed ( Speed ),
-
- // Wishbone compliant core host interface
- .RST_I ( RST_I ),
- .CLK_I ( CLK_I ),
- .STB_I ( STB_I ),
- .CYC_I ( CYC_I ),
- .ADR_I ( ADR_I ),
- .WE_I ( WE_I ),
- .DAT_I ( DAT_I ),
- .DAT_O ( DAT_O ),
- .ACK_O ( ACK_O ),
-
- // User (packet) interface
- .Rx_mac_ra ( Rx_mac_ra ),
- .Rx_mac_rd ( Rx_mac_rd ),
- .Rx_mac_data( Rx_mac_data ),
- .Rx_mac_BE ( Rx_mac_BE ),
- .Rx_mac_pa ( Rx_mac_pa ),
- .Rx_mac_sop ( Rx_mac_sop ),
- .Rx_mac_err ( Rx_mac_err ),
- .Rx_mac_eop ( Rx_mac_eop ),
-
- .Tx_mac_wa ( Tx_mac_wa ),
- .Tx_mac_wr ( Tx_mac_wr ),
- .Tx_mac_data( Tx_mac_data ),
- .Tx_mac_BE ( Tx_mac_BE ),
- .Tx_mac_sop ( Tx_mac_sop ),
- .Tx_mac_eop ( Tx_mac_eop ),
-
- // PHY interface (GMII/MII)
- .Gtx_clk ( Gtx_clk ),
- .Rx_clk ( Rx_clk ),
- .Tx_clk ( Tx_clk ),
- .Tx_er ( Tx_er ),
- .Tx_en ( Tx_en ),
- .Txd ( Txd ),
- .Rx_er ( Rx_er ),
- .Rx_dv ( Rx_dv ),
- .Rxd ( Rxd ),
- .Crs ( Crs ),
- .Col ( Col ),
-
- // MDIO interface (to PHY)
- .Mdio ( Mdio ),
- .Mdc ( Mdc )
- );
-
- reg [15:0] InjectError;
- reg InjectErrorDone;
- reg [15:0] TxError;
- wire Tx_er_Modified;
- wire Tx_en_Modified;
- wire [7:0] Txd_Modified;
-
- Phy_sim U_Phy_sim(
- .Gtx_clk( Gtx_clk ),
- .Rx_clk ( Rx_clk ),
- .Tx_clk ( Tx_clk ),
- .Tx_er ( Tx_er_Modified ),
- .Tx_en ( Tx_en_Modified ),
- .Txd ( Txd_Modified ),
- .Rx_er ( Rx_er ),
- .Rx_dv ( Rx_dv ),
- .Rxd ( Rxd ),
- .Crs ( Crs ),
- .Col ( Col ),
- .Speed ( Speed ),
- .Done ( Done )
- );
-
- integer TxTrackPreAmble;
-
- always @( posedge Reset or posedge Tx_clk )
- if ( Reset )
- TxTrackPreAmble <= 0;
- else
- if ( ~Tx_en )
- TxTrackPreAmble <= 0;
- else
- TxTrackPreAmble <= TxTrackPreAmble + 1;
-
- // Asserted after the Destination MAC address in the packet
- wire TxInPayload = Tx_en & (TxTrackPreAmble > (7+6));
- assign Tx_er_Modified = Tx_er ^ ( TxError[9] & TxInPayload );
- assign Tx_en_Modified = Tx_en ^ ( TxError[8] & TxInPayload );
- assign Txd_Modified = Txd ^ ( TxError[7:0] & {8{TxInPayload}} );
-
- always @( posedge Reset or posedge Tx_clk )
- if ( Reset )
- begin
- InjectError <= 0;
- InjectErrorDone <= 0;
- TxError <= 'b0;
- end
- else
- if ( InjectError )
- begin
- TxError <= InjectError;
- InjectError <= 0;
- InjectErrorDone <= TxInPayload;
- end
- else if ( TxInPayload || InjectErrorDone )
- begin
- TxError <= 8'h00;
- InjectErrorDone <= 0;
- end
-
- //-------------------------------------------------------------------------
- // Track pause on Tx interface
-
- reg TxEnSeenOnce;
- integer TxTrackPause;
-
- always @( posedge Reset or posedge Tx_clk )
- if ( Reset )
- begin
- TxEnSeenOnce <= 0;
- TxTrackPause <= 0;
- end
- else
- if ( Tx_en )
- begin
- if ( TxEnSeenOnce && (TxTrackPause >= 64) ) // 512 bits
- $display( "IDLE period on Tx interface ended after %0d Tx clocks (%0d bits, tick ~ %0d)",
- TxTrackPause,
- (Speed == 4) ? TxTrackPause*8 : TxTrackPause*4,
- (Speed == 4) ? TxTrackPause*8/512 : TxTrackPause*4/512 );
- TxEnSeenOnce <= 1;
- TxTrackPause <= 0;
- end
- else
- TxTrackPause <= TxTrackPause + 1;
-
- //-------------------------------------------------------------------------
- // Host access routines (register read & write)
- //-------------------------------------------------------------------------
-
- task HostInit;
- begin
- RST_I <= 1;
-
- STB_I <= 0;
- CYC_I <= 0;
- ADR_I <= 'b0;
- WE_I <= 0;
- DAT_I <= 'b0;
-
- #100 RST_I <= 0;
-
- // Wait a couple of clock edges before continuing to allow
- // internal logic to get out of reset
- repeat( 2 )
- @( posedge CLK_I );
- end
- endtask
-
- task HostWriteReg;
- input [6:0] Addr;
- input [15:0] Data;
- begin
- @( posedge CLK_I );
- ADR_I <= Addr;
- DAT_I <= Data;
- WE_I <= 1;
- STB_I <= 1;
- CYC_I <= 1;
-
- @( posedge CLK_I );
-
- while ( ~ACK_O )
- @( posedge CLK_I );
-
- STB_I <= 0;
- CYC_I <= 0;
- end
- endtask
-
- task HostReadReg;
- input [6:0] Addr;
- output [15:0] Data;
- begin
- @( posedge CLK_I );
- ADR_I <= Addr;
- WE_I <= 0;
- STB_I <= 1;
- CYC_I <= 1;
-
- @( posedge CLK_I );
-
- while ( ~ACK_O )
- @( posedge CLK_I );
-
- Data = DAT_O;
- STB_I <= 0;
- CYC_I <= 0;
- end
- endtask
-
- //-------------------------------------------------------------------------
- // User interface access routines (packet Tx and Rx)
- //-------------------------------------------------------------------------
-
- `define FIFOSIZE 10000
-
- integer FIFO_WrPtr = 0;
- integer FIFO_RdPtr = 0;
- integer FIFO_ElementCount = 0;
- reg [35:0] FIFO_Data[0:`FIFOSIZE];
-
- function FIFO_Empty;
- input Dummy;
- begin
- if ( FIFO_ElementCount > 0 )
- FIFO_Empty = 0;
- else
- FIFO_Empty = 1;
- end
- endfunction
-
- function FIFO_Full;
- input Dummy;
- begin
- if ( FIFO_ElementCount < `FIFOSIZE )
- FIFO_Full = 0;
- else
- FIFO_Full = 1;
- end
- endfunction
-
- task FIFO_Wr;
- input [35:0] Data;
-
- begin
- if ( !FIFO_Full(0) )
- begin
- FIFO_Data[ FIFO_WrPtr ] = Data;
- FIFO_WrPtr = (FIFO_WrPtr + 1) % `FIFOSIZE;
- FIFO_ElementCount = FIFO_ElementCount + 1;
- end
- else
- begin
- $display( "ERROR: FIFO_Wr() - FIFO overflow!" );
- Error = 1;
- $finish;
- end
- end
- endtask
-
- task FIFO_Rd;
- output [35:0] Data;
-
- begin
- if ( !FIFO_Empty(0) )
- begin
- Data = FIFO_Data[ FIFO_RdPtr ];
- FIFO_RdPtr = (FIFO_RdPtr + 1) % `FIFOSIZE;
- FIFO_ElementCount = FIFO_ElementCount - 1;
- end
- else
- begin
- $display( "ERROR: FIFO_Rd() - Reading from empty FIFO!" );
- Error = 1;
- $finish;
- end
- end
- endtask
-
- //-------------------------------------------------------------------------
-
- `define TXDATALEN 8000
- reg [7:0] TxData[0:`TXDATALEN-1];
- reg [7:0] TxAltData[0:`TXDATALEN-1];
-
- // By default change payload after Ethernet Header
- reg [15:0] TxHeaderLength = 14;
-
- real TxStartTime;
- integer TxPacketCount = 0;
- integer TxByteCount;
-
- task SendPacket;
- input [15:0] Length;
- // 0: Don't write to FIFO, 1: Write to FIFO, 2: Write Alternate to FIFO, 3: Write IGNORE to FIFO
- input [1:0] Wr2FIFO;
-
- reg [15:0] Counter;
- integer TxIndex;
- integer i;
-
- reg [31:0] Tx_fifo_data;
-
- begin
- @( posedge Clk_user ); #1;
-
- TxPacketCount = TxPacketCount + 1;
- TxByteCount = TxByteCount + Length;
-
- Counter=Length;
- TxIndex = 0;
- Tx_mac_sop = 1; // First time
-
- if ( TxStartTime == 0 )
- TxStartTime = $realtime;
-
- while ( Counter>0 )
- begin
- while ( !Tx_mac_wa )
- begin
- Tx_mac_wr = 0;
- @( posedge Clk_user ); #1;
- end
-
- Tx_mac_data[31:24] = TxData[ TxIndex ];
- Tx_mac_data[23:16] = TxData[ TxIndex+1 ];
- Tx_mac_data[15:8] = TxData[ TxIndex+2 ];
- Tx_mac_data[ 7:0] = TxData[ TxIndex+3 ];
-
- // Default take data from regular tx buffer
- Tx_fifo_data = Tx_mac_data;
- if ( Wr2FIFO==2 )
- begin
- // Put content of Alternate Tx buffer on Rx expectancy queue
- if ( (TxIndex+0)<TxHeaderLength )
- Tx_fifo_data[31:24] = TxAltData[ TxIndex ];
- if ( (TxIndex+1)<TxHeaderLength )
- Tx_fifo_data[23:16] = TxAltData[ TxIndex+1 ];
- if ( (TxIndex+2)<TxHeaderLength )
- Tx_fifo_data[15:8] = TxAltData[ TxIndex+2 ];
- if ( (TxIndex+3)<TxHeaderLength )
- Tx_fifo_data[ 7:0] = TxAltData[ TxIndex+3 ];
- end
-
- for ( i=0; i<4; i=i+1 )
- begin
- if ( TxIndex >= TxHeaderLength )
- TxData[ TxIndex ] = TxData[ TxIndex ] + 1;
- TxIndex = TxIndex+1;
- end
-
- if ( Counter<=4 )
- begin
- // Indicate how many bytes are valid
- if ( Counter==4 )
- Tx_mac_BE = 2'b00;
- else
- Tx_mac_BE = Counter;
- Tx_mac_eop = 1;
- end
- else
- begin
- Tx_mac_BE = 2'b00;
- Tx_mac_eop = 0;
- end
-
- casez ( Wr2FIFO )
- 1,
- 2: FIFO_Wr( { Tx_mac_sop, Tx_mac_eop, Tx_mac_BE, Tx_fifo_data } );
- 3: // Ignore
- begin
- FIFO_Wr( { 2'b11, 2'b00, 32'h00000000 } );
- Wr2FIFO = 0;
- end
- endcase
-
- Tx_mac_wr = 1;
-
- if ( Counter >= 4 )
- Counter = Counter - 4;
- else
- Counter = 0;
- @( posedge Clk_user ); #1;
- Tx_mac_sop = 0;
- end
-
- Tx_mac_sop = 1'bx;
- Tx_mac_eop = 1'bx;
- Tx_mac_wr = 0;
- Tx_mac_data = 32'bx;
- Tx_mac_BE = 2'bx;
- end
- endtask
-
- //-------------------------------------------------------------------------
-
- reg Negate_Rx_mac_rd;
-
- always @( posedge Clk_user or posedge Reset )
- if ( Reset )
- Rx_mac_rd <= 0;
- else if ( Rx_mac_ra & ~Negate_Rx_mac_rd )
- Rx_mac_rd <= 1;
- else
- Rx_mac_rd <= 0;
-
- real RxStartTime;
- integer RxPacketCount;
- integer RxByteCount;
-
- reg InPacket;
- integer RxPacketLength;
- reg IgnoreUntilNextERR;
-
- always @( posedge Clk_user or posedge Reset )
- if ( Reset )
- begin
- InPacket = 0;
- RxPacketCount = 0;
- Negate_Rx_mac_rd <= 0;
- IgnoreUntilNextERR = 0;
- end
- else
- begin
- Negate_Rx_mac_rd <= 0;
-
- if ( Rx_mac_pa )
- begin : RxWord
- reg [35:0] RxData;
- reg [35:0] Expected;
- reg [35:0] Mask;
-
- RxData = { Rx_mac_sop, Rx_mac_eop, Rx_mac_BE, Rx_mac_data };
- casez ( Rx_mac_BE )
- 2'b01: Mask = 36'hfff000000;
- 2'b10: Mask = 36'hfffff0000;
- 2'b11: Mask = 36'hfffffff00;
- default: Mask = 36'hfffffffff;
- endcase
-
- // Retrieve expected packet data
-
- if ( !IgnoreUntilNextERR )
- begin
- FIFO_Rd( Expected );
- if ( Expected[35] & Expected[34] )
- begin
- // Both SOP & EOP are asserted in expectancy data
- // - this means that we should ignore all data received until next EOP
- $display( "The payload of this packet will be IGNORED - and an ERROR must be signalled!" );
- IgnoreUntilNextERR = 1;
- end
- end
- if ( IgnoreUntilNextERR )
- Mask = 36'h000000000;
-
- //$display( "DEBUG: RxData=0x%0x, Expected=0x%0x", RxData, Expected );
-
- if ( (RxData & Mask) !== (Expected & Mask) )
- begin
- $display( "ERROR: Receiving unexpected packet data: Got 0x%0x, expected 0x%0x (Mask=0x%0x)",
- RxData, Expected, Mask );
- Error = 1;
- end
-
- if ( InPacket )
- begin
- if ( Rx_mac_eop )
- begin
- // Ensure Rx_mac_rd is negated for one clock
- Negate_Rx_mac_rd <= 1;
- if ( Rx_mac_BE==2'b00 )
- RxPacketLength = RxPacketLength + 4;
- else
- RxPacketLength = RxPacketLength + Rx_mac_BE;
- $display( "Rx packet #%0d of length %0d ends",
- RxPacketCount,
- RxPacketLength );
- RxPacketCount = RxPacketCount + 1;
- RxByteCount = RxByteCount + RxPacketLength;
- InPacket = 0;
- end
- else
- RxPacketLength = RxPacketLength + 4;
- end
- else
- begin
- if ( Rx_mac_sop )
- begin
- RxPacketLength = 4;
- $display( "Rx packet #%0d begins: 0x%08x", RxPacketCount, Rx_mac_data );
- InPacket = 1;
- if ( RxStartTime == 0 )
- RxStartTime = $realtime;
- end
- else
- begin
- $display( "ERROR: Unexpectedly reading from Rx FIFO while not receiving a packet!" );
- Error = 1;
- end
- end
-
- if ( Rx_mac_err )
- begin
- if ( !Rx_mac_eop )
- begin
- $display( "ERROR: Rx_mac_err was asserted without Rx_mac_eop also being asserted!" );
- Error = 1;
- end
- if ( IgnoreUntilNextERR )
- $display( "Info: Rx_mac_err was asserted as expected!" );
- else
- begin
- $display( "ERROR: Rx_mac_err was unexpectedly asserted!" );
- Error = 1;
- end
- IgnoreUntilNextERR = 0;
- end
- end
- end
-
- //-------------------------------------------------------------------------
- // Script handling
- //-------------------------------------------------------------------------
-
- integer PC;
-
- task ScriptWriteReg;
- input [15:0] Addr;
- input [15:0] Data;
-
- begin
- $display( "WriteReg( 0x%04x, 0x%04x )", Addr, Data );
- HostWriteReg( Addr, Data );
- end
- endtask
-
- task ScriptReadReg;
- input [15:0] Addr;
-
- reg [15:0] Data;
-
- begin
- $write( "ReadReg( 0x%04x ): ", Addr );
- HostReadReg( Addr, Data );
- $display( "0x%04x", Data );
- end
- endtask
-
- task ScriptReadRegAndMatch;
- input [15:0] Addr;
- input [15:0] Data;
- input [15:0] Mask;
-
- reg [15:0] Read;
-
- begin
- $write( "ReadRegAndMatch( 0x%04x, 0x%04x, 0x%04x ): ", Addr, Data, Mask );
-
- HostReadReg( Addr, Read );
- $display( "0x%04x, masked=0x%04x", Read, Read & Mask );
-
- if ( Data !== (Read & Mask) )
- begin
- $display( "Error: Unexpected data read" );
- Error = 1;
- end
- end
- endtask
-
- integer RxExpectPacketCount = 0;
-
- task ScriptSendPacket;
- input [15:0] Length;
- // 0: Don't receive, 1: Receive & match, 2: Receive & match alternate, 3: Receive & ignore
- input [1:0] ExpectToRx;
-
- begin
- $display( "ScriptSendPacket( 0x%04x, %0d )", Length, ExpectToRx );
- SendPacket( Length, ExpectToRx );
- if ( ExpectToRx != 0 )
- RxExpectPacketCount = RxExpectPacketCount + 1;
- end
- endtask
-
- `define SCRIPTLEN 10000
- integer i;
- reg [7:0] Script[0:`SCRIPTLEN-1];
-
- function [15:0] Get16bit;
- input Dummy;
-
- reg [15:0] Data;
-
- begin
- Data[15:8] = Script[PC];
- Data[7:0] = Script[PC+1];
- PC = PC+2;
-
- Get16bit = Data;
- end
- endfunction
-
- task ExecuteScript;
-
- reg [7:0] OpCode;
- reg [15:0] Addr;
- reg [15:0] Data;
- reg [15:0] Length;
- reg [15:0] Count;
- reg [15:0] Mask;
-
- reg ScriptDone;
-
- begin
- ScriptDone = 0;
- Error = 0;
- PC = 0;
-
- while ( !ScriptDone )
- begin
- OpCode = Script[PC];
- //$write( "PC=%0d, OpCode=%02x: ", PC, OpCode );
- PC = PC+1;
-
- casez ( OpCode )
- 8'h00: // NOP
- begin
-// $display( "NOP" );
- #10;
- end
- 8'h01: // Write
- begin
- Addr = Get16bit(i);
- Data = Get16bit(i);
- ScriptWriteReg( Addr, Data );
- end
- 8'h02: // Read
- begin
- Addr = Get16bit(i);
- ScriptReadReg( Addr );
- end
- 8'h03: // Read & match
- begin
- Addr = Get16bit(i);
- Data = Get16bit(i);
- Mask = Get16bit(i);
- ScriptReadRegAndMatch( Addr, Data, Mask );
- end
-
- 8'h0f: // Delay
- begin
- Count = Get16bit(i);
- $display( "Delay %0d", Count );
- while ( Count > 0 )
- begin
- #10;
- Count = Count - 1;
- end
- end
-
- 8'h10: // Setup Tx Data
- begin
- Addr = Get16bit(i);
- Length = Get16bit(i);
- $write( "TxData( 0x%04x ), length=%0d: ", Addr, Length );
- while ( Length != 0 )
- begin
- TxData[Addr] = Script[PC];
- $write( " 0x%02x", Script[PC] );
- PC = PC + 1;
- Addr = Addr + 1;
- Length = Length - 1;
- end
- $display( "" );
- end
-
- 8'h11: // Setup Alternative Tx Data
- begin
- Addr = Get16bit(i);
- Length = Get16bit(i);
- $write( "TxAltData( 0x%04x ), length=%0d: ", Addr, Length );
- while ( Length != 0 )
- begin
- TxAltData[Addr] = Script[PC];
- $write( " 0x%02x", Script[PC] );
- PC = PC + 1;
- Addr = Addr + 1;
- Length = Length - 1;
- end
- $display( "" );
- end
-
- 8'h20: // Transmit packet - and put it on Rx expectancy queue
- begin
- Length = Get16bit(i); // Length in bytes
- Count = Get16bit(i); // Number of times
- while ( Count != 0 )
- begin
- ScriptSendPacket( Length, 1 );
- Count = Count - 1;
- end
- end
-
- 8'h21: // Transmit packet - but DON'T put it on Rx expectancy queue
- begin
- Length = Get16bit(i); // Length in bytes
- Count = Get16bit(i); // Number of times
- while ( Count != 0 )
- begin
- ScriptSendPacket( Length, 0 );
- Count = Count - 1;
- end
- end
-
- 8'h22: // Wait
- begin : OpCode22
- reg NoTimeOut;
- Count = Get16bit(i); // Timeout in ns
- if ( Count==0 )
- NoTimeOut = 1;
- else
- NoTimeOut = 0;
-
- $display( "Waiting for # of Rx packets = # of Tx packets..." );
- $display( "Timeout = %0d ns - Current # Rx =%0d, Expected=%0d",
- Count, RxPacketCount, RxExpectPacketCount );
-
- while( (NoTimeOut || (Count != 0)) && ( RxExpectPacketCount != RxPacketCount ) && !Error )
- begin
- #1;
- if ( !NoTimeOut )
- Count = Count - 1;
- //$display( "NoTimeOut=%0d, Count=%0d", NoTimeOut, Count );
- end
-
- if ( !Error )
- if ( RxExpectPacketCount != RxPacketCount )
- begin
- $display( "ERROR: Timeout waiting for Rx packet(s)!" );
- ScriptDone = 1;
- Error = 1;
- end
- else
- $display( "...Done waiting (time remaining = %0d ns)!", Count );
- end
-
- 8'h23: // Inject bit error in Tx packet
- begin
- InjectError = Get16bit(i); // Get bit error pattern
- $display( "Injecting a single bit-error in Tx packet: TxEr=%0d, TxEn=%0d, TxD=0x%02h (0x%03h)",
- InjectError[9], InjectError[8], InjectError[7:0], InjectError );
- end
-
- 8'h24: // Store internally generated PAUSE frame in Rx expect queue
- begin
- Count = Get16bit(i); // Timeout in ns
- $display( "Generating PAUSE frame (tick=%0d) on Rx expect queue", Count );
- RxExpectPacketCount = RxExpectPacketCount + 1;
- FIFO_Wr( { 1'b1, 1'b0, 2'b00, 32'h0180c200 } );
- FIFO_Wr( { 1'b0, 1'b0, 2'b00, 16'h0001, 16'h0000 } );
- FIFO_Wr( { 1'b0, 1'b0, 2'b00, 32'h00000000 } );
- FIFO_Wr( { 1'b0, 1'b0, 2'b00, 32'h88080001 } );
- FIFO_Wr( { 1'b0, 1'b0, 2'b00, Count, 16'h0000 } );
- FIFO_Wr( { 1'b0, 1'b0, 2'b00, 32'h00000000 } );
- FIFO_Wr( { 1'b0, 1'b0, 2'b00, 32'h00000000 } );
- FIFO_Wr( { 1'b0, 1'b0, 2'b00, 32'h00000000 } );
- FIFO_Wr( { 1'b0, 1'b0, 2'b00, 32'h00000000 } );
- FIFO_Wr( { 1'b0, 1'b0, 2'b00, 32'h00000000 } );
- FIFO_Wr( { 1'b0, 1'b0, 2'b00, 32'h00000000 } );
- FIFO_Wr( { 1'b0, 1'b0, 2'b00, 32'h00000000 } );
- FIFO_Wr( { 1'b0, 1'b0, 2'b00, 32'h00000000 } );
- FIFO_Wr( { 1'b0, 1'b0, 2'b00, 32'h00000000 } );
- FIFO_Wr( { 1'b0, 1'b1, 2'b00, 32'h00000000 } );
- end
-
- 8'h25: // Transmit packet - and indicate that it must be IGNORED upon reception
- begin
- Length = Get16bit(i); // Length in bytes
- Count = Get16bit(i); // Number of times
- while ( Count != 0 )
- begin
- ScriptSendPacket( Length, 3 );
- Count = Count - 1;
- end
- end
-
- 8'h26: // Transmit packet - and put it on expectancy queue with Alternate header!
- begin
- Length = Get16bit(i); // Length in bytes
- Count = Get16bit(i); // Number of times
- while ( Count != 0 )
- begin
- ScriptSendPacket( Length, 2 );
- Count = Count - 1;
- end
- end
-
- 8'hff: // Halt
- begin
- $display( "HALT" );
- ScriptDone = 1;
- Done = 1;
- end
-
- default: // Unknown opcode
- begin
- $display( "Unknown instruction encountered @ PC=%0d: OpCode=0x%02x", PC-1, OpCode );
- Error = 1;
- end
-
- endcase
-
- if ( Error )
- begin
- ScriptDone = 1;
- Done = 1;
- end
- end
-
- if ( Error )
- $display( "ERROR: Test failed!");
- else
- begin : ScriptSuccess
- real TxTimeElapsed;
- real RxTimeElapsed;
- real ReferenceTime;
-
- ReferenceTime = $realtime;
- #1;
- ReferenceTime = $realtime - ReferenceTime;
-
- TxTimeElapsed = $realtime - TxStartTime;
- RxTimeElapsed = $realtime - RxStartTime;
-
- $display( "TxStartTime=%0e, Now=%0e", TxStartTime, $realtime );
- $display( "RxStartTime=%0e, Now=%0e", RxStartTime, $realtime );
-
- $display( "Tx stats: %0d packet(s) send, total of %0d bytes in %0e ns ~ %1.2f Mbps",
- TxPacketCount, TxByteCount, TxTimeElapsed, TxByteCount*8*1e3/TxTimeElapsed );
- $display( "Rx stats: %0d packet(s) received, total of %0d bytes in %0e ns ~ %1.2f Mbps",
- RxPacketCount, RxByteCount, RxTimeElapsed, RxByteCount*8*1e3/RxTimeElapsed );
- $display( "Test succeeded!");
- end
-
- end
- endtask
-
- //-------------------------------------------------------------------------
- // Generate all clocks
- //-------------------------------------------------------------------------
-
- // GMII master clock (125 MHz)
- initial
- begin
- #10;
- while ( !Done )
- begin
- #4 Clk_125M = 0;
- #4 Clk_125M = 1;
- end
- end
-
- // User (packet) interface clock (100 MHz)
- initial
- begin
- #10;
- while ( !Done )
- begin
- #5 Clk_user = 0;
- #5 Clk_user = 1;
- end
- end
-
- // Wishbone host interface clock (50 MHz)
- initial
- begin
- #10;
- while ( !Done )
- begin
- #10 CLK_I = 0;
- #10 CLK_I = 1;
- end
- end
-
- //-------------------------------------------------------------------------
-
- initial
- begin
- if ( $test$plusargs( "vcd" ) )
- begin
- $display( "Turning VCD data dump on" );
- $dumpfile();
- $dumpvars( 0 ); // Dump all signals in entire design
- end
- end
-
- //-------------------------------------------------------------------------
-
- reg [1023:0] ScriptFile;
-
- initial
- begin
- HostInit;
-
- TxStartTime = 0;
- RxStartTime = 0;
- TxByteCount = 0;
- RxByteCount = 0;
-
- for ( i=0; i<`TXDATALEN; i=i+1 )
- TxData[i] = (i & 8'hff);
-
- // Fill script memory with HALTs
- for ( i=0; i<`SCRIPTLEN; i=i+1 )
- Script[i] = 8'hff;
-
- if ( !$value$plusargs( "script=%s", ScriptFile ) )
- begin
- $display( "Using default script file" );
- ScriptFile = "test.scr";
- end
-
- $readmemh( ScriptFile, Script );
-
-// for ( i=0; i<40; i=i+1 )
-// $display( "Script[%0d]=0x%02x", i, Script[i] );
-
- #10;
-
- ExecuteScript;
- end
-
-endmodule
diff --git a/eth/bench/verilog/test.scr b/eth/bench/verilog/test.scr deleted file mode 100644 index 2ad127d31..000000000 --- a/eth/bench/verilog/test.scr +++ /dev/null @@ -1,23 +0,0 @@ -// This tests just runs trough a couple of different packet lengths
-
-// Read from register 24 to confirm that Rx CRC check is enabled
-03 00 18 00 01 ff ff
-
-// Set speed to 1000 Mbps
-01 00 22 00 04
-
-// Setup Tx and Rx MAC addresses and type field to "IP"
-// Set Tx Data at offset 0, length 14 to 123456789ABC CBA987654321 0800
-10 00 00 00 0E 12 34 56 78 9A BC CB A9 87 65 43 21 08 00
-
-// Transmit a 320-byte frame 1 time - and expect it to be received again!
-20 01 40 00 01
-
-// Transmit a 80-byte frame 1 time - and expect it to be received again!
-20 00 50 00 01
-
-// Wait (indefinitely) for missing Rx packets
-22 00 00
-
-// Halt
-FF
diff --git a/eth/bench/verilog/txmac.scr b/eth/bench/verilog/txmac.scr deleted file mode 100644 index caa7db594..000000000 --- a/eth/bench/verilog/txmac.scr +++ /dev/null @@ -1,93 +0,0 @@ -// Read from register 24 to confirm that Rx CRC check is enabled
-03 00 18 00 01 ff ff
-
-// Set speed to 1000 Mbps
-01 00 22 00 04
-
-// Write MAC address 12 35 56 78 9A BC to Rx Address buffer
-01 00 10 00 00
-01 00 0f 00 12
-01 00 11 00 01
-01 00 11 00 00
-01 00 10 00 01
-01 00 0f 00 34
-01 00 11 00 01
-01 00 11 00 00
-01 00 10 00 02
-01 00 0f 00 56
-01 00 11 00 01
-01 00 11 00 00
-01 00 10 00 03
-01 00 0f 00 78
-01 00 11 00 01
-01 00 11 00 00
-01 00 10 00 04
-01 00 0f 00 9A
-01 00 11 00 01
-01 00 11 00 00
-01 00 10 00 05
-01 00 0f 00 BC
-01 00 11 00 01
-01 00 11 00 00
-
-// Write 1 to register 14, MAC_rx_add_chk_en
-// This turns on the Rx Destination MAC address filter
-01 00 0e 00 01
-
-// Setup Tx and Rx MAC addresses and type field to "IP"
-// Set Tx Data at offset 0, length 14 to 123456789ABC CBA987654321 0800
-// (i.e. Destination MAC address is 123456789ABC matching the above)
-10 00 00 00 0E 12 34 56 78 9A BC CB A9 87 65 43 21 08 00
-
-// Setup Alternate Tx and Rx MAC addresses and type field to "IP"
-// Set Tx Data at offset 0, length 14 to 123456789ABC 112233445566 0800
-// (i.e. Destination MAC address is 123456789ABC matching the above)
-11 00 00 00 0E 12 34 56 78 9A BC 11 22 33 44 55 66 08 00
-
-// Transmit a 60-byte frame 3 times - and expect them to be received again!
-20 00 3C 00 03
-
-// Wait (indefinitely) for missing Rx packets
-22 00 00
-
-// Write MAC address 11 22 33 44 55 66 to Tx MAC Source Address buffer
-01 00 09 00 00
-01 00 08 00 11
-01 00 0a 00 01
-01 00 0a 00 00
-01 00 09 00 01
-01 00 08 00 22
-01 00 0a 00 01
-01 00 0a 00 00
-01 00 09 00 02
-01 00 08 00 33
-01 00 0a 00 01
-01 00 0a 00 00
-01 00 09 00 03
-01 00 08 00 44
-01 00 0a 00 01
-01 00 0a 00 00
-01 00 09 00 04
-01 00 08 00 55
-01 00 0a 00 01
-01 00 0a 00 00
-01 00 09 00 05
-01 00 08 00 66
-01 00 0a 00 01
-01 00 0a 00 00
-
-// Transmit a 60 byte frame 3 times - and expect them to be received again!
-20 00 3C 00 03
-
-// Wait (indefinitely) for missing Rx packets
-22 00 00
-
-// Write 1 to register 7, MAC_tx_add_en
-// This turns on the Tx Source MAC address replacement mechanism
-01 00 07 00 01
-
-// Transmit a 60 byte frame 3 times - and expect them to be received again with Alternate header!
-26 00 3C 00 03
-
-// Wait (indefinitely) for missing Rx packets
-22 00 00
diff --git a/eth/bench/verilog/xlnx_glbl.v b/eth/bench/verilog/xlnx_glbl.v deleted file mode 100644 index 662a60e35..000000000 --- a/eth/bench/verilog/xlnx_glbl.v +++ /dev/null @@ -1,29 +0,0 @@ -module xlnx_glbl
-(
- GSR,
- GTS
-);
-
- //--------------------------------------------------------------------------
- // Parameters
- //--------------------------------------------------------------------------
-
- //--------------------------------------------------------------------------
- // IO declarations
- //--------------------------------------------------------------------------
-
- output GSR;
- output GTS;
-
- //--------------------------------------------------------------------------
- // Local declarations
- //--------------------------------------------------------------------------
-
- //--------------------------------------------------------------------------
- // Internal declarations
- //--------------------------------------------------------------------------
-
- assign GSR = 0;
- assign GTS = 0;
-
-endmodule
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