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| author | Nick Foster <nick@ettus.com> | 2012-01-04 17:06:23 -0800 |
|---|---|---|
| committer | Josh Blum <josh@joshknows.com> | 2012-01-04 21:43:15 -0800 |
| commit | 97bd77ef81aa5e04383fa2cdef9af1ca504da472 (patch) | |
| tree | e192269ce70fb724bba9d86e2d4f474cb143ffb0 /eth/bench/verilog/test.scr | |
| parent | a34559fc834cb7f9f25f0711bf26c5eeb269e734 (diff) | |
| download | uhd-97bd77ef81aa5e04383fa2cdef9af1ca504da472.tar.gz uhd-97bd77ef81aa5e04383fa2cdef9af1ca504da472.tar.bz2 uhd-97bd77ef81aa5e04383fa2cdef9af1ca504da472.zip | |
N210 R4 should be using LVDS TX clock, not CMOS.release_003_003_002
Diffstat (limited to 'eth/bench/verilog/test.scr')
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