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| author | Matt Ettus <matt@ettus.com> | 2009-09-10 23:11:44 -0700 |
|---|---|---|
| committer | Matt Ettus <matt@ettus.com> | 2009-09-10 23:11:44 -0700 |
| commit | 7bdf0a5536d1e53a9ca9a53640298a7c26539316 (patch) | |
| tree | 15d9f4efc1e39e9771150cb3727b4461860a3f54 /eth/bench/verilog/test.scr | |
| parent | 2517c53048ad7913212096dde9eb495b2f5391ee (diff) | |
| download | uhd-7bdf0a5536d1e53a9ca9a53640298a7c26539316.tar.gz uhd-7bdf0a5536d1e53a9ca9a53640298a7c26539316.tar.bz2 uhd-7bdf0a5536d1e53a9ca9a53640298a7c26539316.zip | |
Remove old mac. Good riddance.
Diffstat (limited to 'eth/bench/verilog/test.scr')
| -rw-r--r-- | eth/bench/verilog/test.scr | 23 |
1 files changed, 0 insertions, 23 deletions
diff --git a/eth/bench/verilog/test.scr b/eth/bench/verilog/test.scr deleted file mode 100644 index 2ad127d31..000000000 --- a/eth/bench/verilog/test.scr +++ /dev/null @@ -1,23 +0,0 @@ -// This tests just runs trough a couple of different packet lengths
-
-// Read from register 24 to confirm that Rx CRC check is enabled
-03 00 18 00 01 ff ff
-
-// Set speed to 1000 Mbps
-01 00 22 00 04
-
-// Setup Tx and Rx MAC addresses and type field to "IP"
-// Set Tx Data at offset 0, length 14 to 123456789ABC CBA987654321 0800
-10 00 00 00 0E 12 34 56 78 9A BC CB A9 87 65 43 21 08 00
-
-// Transmit a 320-byte frame 1 time - and expect it to be received again!
-20 01 40 00 01
-
-// Transmit a 80-byte frame 1 time - and expect it to be received again!
-20 00 50 00 01
-
-// Wait (indefinitely) for missing Rx packets
-22 00 00
-
-// Halt
-FF
|