Remove old mac. Good riddance.

1 files changed, 0 insertions, 45 deletions

diff --git a/eth/bench/verilog/pause.scr b/eth/bench/verilog/pause.scr
deleted file mode 100644
index be74027e3..000000000
--- a/eth/bench/verilog/pause.scr
+++ /dev/null
@@ -1,45 +0,0 @@
-// This test demonstrates the ability to transmit a PAUSE frame, and the effect of

-// a PAUSE frame on the receiver

-

-// Read from register 24 to confirm that Rx CRC check is enabled

-03 00 18 00 01 ff ff

-

-// Set speed to 1000 Mbps

-01 00 22 00 04

-

-// Setup Tx and Rx MAC addresses and type field to "IP"

-// Set Tx Data at offset 0, length 14 to 123456789ABC CBA987654321 0800

-10 00 00 00 0E 12 34 56 78 9A BC CB A9 87 65 43 21 08 00

-

-// Set PAUSE quanta to 256 - corresponding to a pause of 256x512 = 128Kb = 16KB

-01 00 03 01 00

-

-// Enable the transmitter to send a PAUSE frame

-01 00 02 00 01

-

-// Enable the transmitter to react to received PAUSE frames

-01 00 0b 00 01

-

-// Expect to receive a PAUSE frame with quanta 256

-24 01 00

-

-// Transmit a 512-byte frame 1 time - and expect it to be received again!

-20 02 00 00 01

-

-// Request the transmission of a PAUSE frame - it will loopback to ourselves and delay

-// further transmission for a period of 16 KB, causing a significant (visible) delay

-// between first and second 512-byte frame!

-01 00 0c 00 01

-

-// - now this second time, we will experience a delay

-// Transmit a 512-byte frame 1 time - and expect it to be received again!

-20 02 00 00 01

-// - and a final 3rd time

-// Transmit a 512-byte frame 1 time - and expect it to be received again!

-20 02 00 00 01

-

-// Wait (indefinitely) for missing Rx packets

-22 00 00 

-

-// Halt

-FF