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author | Johnathan Corgan <jcorgan@corganenterprises.com> | 2009-10-01 11:00:25 -0700 |
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committer | Johnathan Corgan <jcorgan@corganenterprises.com> | 2009-10-01 11:07:59 -0700 |
commit | 1ff74777e47f3a2edefc5154484f2bdcb86c1a13 (patch) | |
tree | 04f94ef4f7f06a210f7532592829332c7f2621f0 /eth/bench/verilog/pause.scr | |
parent | 7b8f65256b5ea300187ebb6a359df2fa707a295d (diff) | |
parent | 42fc55415af499980901c7787f44c7e74b4a9ce1 (diff) | |
download | uhd-1ff74777e47f3a2edefc5154484f2bdcb86c1a13.tar.gz uhd-1ff74777e47f3a2edefc5154484f2bdcb86c1a13.tar.bz2 uhd-1ff74777e47f3a2edefc5154484f2bdcb86c1a13.zip |
Merge branch 'new_eth' of http://gnuradio.org/git/matt into master
* 'new_eth' of http://gnuradio.org/git/matt: (42 commits)
Fix warnings, mostly from implicitly defined wires or unspecified widths
fullchip sim now compiles again, after moving eth and models over to new simple_gemac
remove unused opencores
remove debugging code
no idea where this came from, it shouldn't be here
Copied wb_1master back from quad radio
Remove old mac. Good riddance.
remove unused port
More xilinx fifos, more clean up of our fifos
might as well use a cascade fifo to help timing and give a little more capacity
fix a typo which caused tx glitches
Untested fixes for getting serdes onto the new fifo system. Compiles, at least
Implement Eth flow control using pause frames
parameterized fifo sizes, some reformatting
remove unused old style fifo
allow control of whether or not to honor flow control, adds some debug lines
debug the rx side
no longer used, replaced by newfifo version
remove special last_line adjustment from ethernet port
Firmware now inserts mac source address value in each frame.
...
Diffstat (limited to 'eth/bench/verilog/pause.scr')
-rw-r--r-- | eth/bench/verilog/pause.scr | 45 |
1 files changed, 0 insertions, 45 deletions
diff --git a/eth/bench/verilog/pause.scr b/eth/bench/verilog/pause.scr deleted file mode 100644 index be74027e3..000000000 --- a/eth/bench/verilog/pause.scr +++ /dev/null @@ -1,45 +0,0 @@ -// This test demonstrates the ability to transmit a PAUSE frame, and the effect of
-// a PAUSE frame on the receiver
-
-// Read from register 24 to confirm that Rx CRC check is enabled
-03 00 18 00 01 ff ff
-
-// Set speed to 1000 Mbps
-01 00 22 00 04
-
-// Setup Tx and Rx MAC addresses and type field to "IP"
-// Set Tx Data at offset 0, length 14 to 123456789ABC CBA987654321 0800
-10 00 00 00 0E 12 34 56 78 9A BC CB A9 87 65 43 21 08 00
-
-// Set PAUSE quanta to 256 - corresponding to a pause of 256x512 = 128Kb = 16KB
-01 00 03 01 00
-
-// Enable the transmitter to send a PAUSE frame
-01 00 02 00 01
-
-// Enable the transmitter to react to received PAUSE frames
-01 00 0b 00 01
-
-// Expect to receive a PAUSE frame with quanta 256
-24 01 00
-
-// Transmit a 512-byte frame 1 time - and expect it to be received again!
-20 02 00 00 01
-
-// Request the transmission of a PAUSE frame - it will loopback to ourselves and delay
-// further transmission for a period of 16 KB, causing a significant (visible) delay
-// between first and second 512-byte frame!
-01 00 0c 00 01
-
-// - now this second time, we will experience a delay
-// Transmit a 512-byte frame 1 time - and expect it to be received again!
-20 02 00 00 01
-// - and a final 3rd time
-// Transmit a 512-byte frame 1 time - and expect it to be received again!
-20 02 00 00 01
-
-// Wait (indefinitely) for missing Rx packets
-22 00 00
-
-// Halt
-FF
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