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| author | Johnathan Corgan <jcorgan@corganenterprises.com> | 2009-10-01 11:00:25 -0700 |
|---|---|---|
| committer | Johnathan Corgan <jcorgan@corganenterprises.com> | 2009-10-01 11:07:59 -0700 |
| commit | 1ff74777e47f3a2edefc5154484f2bdcb86c1a13 (patch) | |
| tree | 04f94ef4f7f06a210f7532592829332c7f2621f0 /eth/bench/verilog/mdio.scr | |
| parent | 7b8f65256b5ea300187ebb6a359df2fa707a295d (diff) | |
| parent | 42fc55415af499980901c7787f44c7e74b4a9ce1 (diff) | |
| download | uhd-1ff74777e47f3a2edefc5154484f2bdcb86c1a13.tar.gz uhd-1ff74777e47f3a2edefc5154484f2bdcb86c1a13.tar.bz2 uhd-1ff74777e47f3a2edefc5154484f2bdcb86c1a13.zip | |
Merge branch 'new_eth' of http://gnuradio.org/git/matt into master
* 'new_eth' of http://gnuradio.org/git/matt: (42 commits)
Fix warnings, mostly from implicitly defined wires or unspecified widths
fullchip sim now compiles again, after moving eth and models over to new simple_gemac
remove unused opencores
remove debugging code
no idea where this came from, it shouldn't be here
Copied wb_1master back from quad radio
Remove old mac. Good riddance.
remove unused port
More xilinx fifos, more clean up of our fifos
might as well use a cascade fifo to help timing and give a little more capacity
fix a typo which caused tx glitches
Untested fixes for getting serdes onto the new fifo system. Compiles, at least
Implement Eth flow control using pause frames
parameterized fifo sizes, some reformatting
remove unused old style fifo
allow control of whether or not to honor flow control, adds some debug lines
debug the rx side
no longer used, replaced by newfifo version
remove special last_line adjustment from ethernet port
Firmware now inserts mac source address value in each frame.
...
Diffstat (limited to 'eth/bench/verilog/mdio.scr')
| -rw-r--r-- | eth/bench/verilog/mdio.scr | 52 |
1 files changed, 0 insertions, 52 deletions
diff --git a/eth/bench/verilog/mdio.scr b/eth/bench/verilog/mdio.scr deleted file mode 100644 index 8ad9969b9..000000000 --- a/eth/bench/verilog/mdio.scr +++ /dev/null @@ -1,52 +0,0 @@ -// Read from register 24 to confirm that Rx CRC check is enabled
-03 00 18 00 01 ff ff
-
-// Set speed to 1000 Mbps
-01 00 22 00 04
-
-// Set MDIO clock (MDC) divider to 4 to speed up test
-01 00 23 00 04
-03 00 23 00 04 ff ff
-
-// Check default (reset) values in new (added) MDIO registers
-//03 00 23 00 64 ff ff
-03 00 24 00 00 ff ff
-03 00 25 00 00 ff ff
-03 00 26 00 00 ff ff
-03 00 27 00 00 ff ff
-03 00 28 00 00 ff ff
-
-// Set RGAD=0x00 (all zeroes), FIAD=0x1f (all ones), check it
-// - these values allows easy recognition in the waveform
-01 00 25 00 1f
-03 00 25 00 1f ff ff
-
-// Now start the read operation by writing a 1 to the MIICOMMAND[1] - RSTAT
-01 00 24 00 02
-03 00 24 00 02 ff ff
-
-// Delay for 768 NOP
-0F 03 00
-
-// Check that the read operation has completed
-03 00 28 00 00 ff ff
-
-// Set RGAD=0x1f (all ones), FIAD=0x00 (all zeroes), check it
-// - these values allows easy recognition in the waveform
-01 00 25 1f 00
-03 00 25 1f 00 ff ff
-// Set MIITX_DATA = 0xAAAA, check it
-01 00 26 AA AA
-03 00 26 AA AA ff ff
-// Check MIISTATUS - must still be zero
-03 00 28 00 00 ff ff
-
-// Now start the write operation by writing a 1 to the MIICOMMAND[2] - WCTRLDATA
-01 00 24 00 04
-03 00 24 00 04 ff ff
-
-// Delay for 768 NOP
-0F 03 00
-
-// Check that the write operation has completed
-03 00 28 00 00 ff ff
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