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| author | jcorgan <jcorgan@221aa14e-8319-0410-a670-987f0aec2ac5> | 2008-09-08 01:00:12 +0000 |
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| committer | jcorgan <jcorgan@221aa14e-8319-0410-a670-987f0aec2ac5> | 2008-09-08 01:00:12 +0000 |
| commit | 61f2f0214c5999ea42a368a4fc99f03d8eb28d1e (patch) | |
| tree | e7e24a9adc05ff1422fe3ada9926a51634741b47 /eth/bench/verilog/host_sim.v | |
| download | uhd-61f2f0214c5999ea42a368a4fc99f03d8eb28d1e.tar.gz uhd-61f2f0214c5999ea42a368a4fc99f03d8eb28d1e.tar.bz2 uhd-61f2f0214c5999ea42a368a4fc99f03d8eb28d1e.zip | |
Merged r9433:9527 from features/gr-usrp2 into trunk. Adds usrp2 and gr-usrp2 top-level components. Trunk passes distcheck with mb-gcc installed, but currently not without them. The key issue is that when mb-gcc is not installed, the build system skips over the usrp2/firmware directory, and the firmware include files don't get put into the dist tarball. But we can't do the usual DIST_SUBDIRS method as the firmware is a subpackage.
git-svn-id: http://gnuradio.org/svn/gnuradio/trunk@9528 221aa14e-8319-0410-a670-987f0aec2ac5
Diffstat (limited to 'eth/bench/verilog/host_sim.v')
| -rw-r--r-- | eth/bench/verilog/host_sim.v | 82 |
1 files changed, 82 insertions, 0 deletions
diff --git a/eth/bench/verilog/host_sim.v b/eth/bench/verilog/host_sim.v new file mode 100644 index 000000000..55abb8508 --- /dev/null +++ b/eth/bench/verilog/host_sim.v @@ -0,0 +1,82 @@ +module host_sim(
+ input Reset,
+ input Clk_reg,
+ output reg CSB,
+ output reg WRB,
+ output reg CPU_init_end,
+ output reg [15:0] CD_in,
+ input [15:0] CD_out,
+ output reg [7:0] CA
+);
+
+////////////////////////////////////////
+
+task CPU_init;
+ begin
+ CA = 0;
+ CD_in = 0;
+ WRB = 1;
+ CSB = 1;
+ end
+endtask
+
+////////////////////////////////////////
+
+task CPU_wr;
+ input [6:0] Addr;
+ input [15:0] Data;
+ begin
+ CA = {Addr,1'b0};
+ CD_in = Data;
+ WRB = 0;
+ CSB = 0;
+ #20;
+ CA = 0;
+ CD_in = 0;
+ WRB = 1;
+ CSB = 1;
+ #20;
+ end
+endtask
+
+/////////////////////////////////////////
+
+task CPU_rd;
+ input [6:0] Addr;
+ begin
+ CA = {Addr,1'b0};
+ WRB = 1;
+ CSB = 0;
+ #20;
+ CA = 0;
+ WRB = 1;
+ CSB = 1;
+ #20;
+ end
+endtask
+
+/////////////////////////////////////////
+
+integer i;
+
+reg [31:0] CPU_data [255:0];
+reg [7:0] write_times;
+reg [7:0] write_add;
+reg [15:0] write_data;
+
+initial
+ begin
+ CPU_init;
+ CPU_init_end=0;
+ //$readmemh("../data/CPU.vec",CPU_data);
+ //{write_times,write_add,write_data}=CPU_data[0];
+ {write_times,write_add,write_data}='b0;
+ #90;
+ for (i=0;i<write_times;i=i+1)
+ begin
+ {write_times,write_add,write_data}=CPU_data[i];
+ CPU_wr(write_add[6:0],write_data);
+ end
+ CPU_init_end=1;
+ end
+endmodule
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