diff options
author | Matt Ettus <matt@ettus.com> | 2009-09-10 23:11:44 -0700 |
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committer | Matt Ettus <matt@ettus.com> | 2009-09-10 23:11:44 -0700 |
commit | 7bdf0a5536d1e53a9ca9a53640298a7c26539316 (patch) | |
tree | 15d9f4efc1e39e9771150cb3727b4461860a3f54 /eth/bench/verilog/files.lst | |
parent | 2517c53048ad7913212096dde9eb495b2f5391ee (diff) | |
download | uhd-7bdf0a5536d1e53a9ca9a53640298a7c26539316.tar.gz uhd-7bdf0a5536d1e53a9ca9a53640298a7c26539316.tar.bz2 uhd-7bdf0a5536d1e53a9ca9a53640298a7c26539316.zip |
Remove old mac. Good riddance.
Diffstat (limited to 'eth/bench/verilog/files.lst')
-rw-r--r-- | eth/bench/verilog/files.lst | 42 |
1 files changed, 0 insertions, 42 deletions
diff --git a/eth/bench/verilog/files.lst b/eth/bench/verilog/files.lst deleted file mode 100644 index 6175a4d43..000000000 --- a/eth/bench/verilog/files.lst +++ /dev/null @@ -1,42 +0,0 @@ -../../rtl/verilog/MAC_rx/Broadcast_filter.v
-../../rtl/verilog/MAC_rx/CRC_chk.v
-../../rtl/verilog/MAC_rx/MAC_rx_add_chk.v
-../../rtl/verilog/MAC_rx/MAC_rx_ctrl.v
-../../rtl/verilog/MAC_rx/MAC_rx_FF.v
-
-../../rtl/verilog/MAC_tx/CRC_gen.v
-../../rtl/verilog/MAC_tx/flow_ctrl.v
-../../rtl/verilog/MAC_tx/MAC_tx_addr_add.v
-../../rtl/verilog/MAC_tx/MAC_tx_ctrl.v
-../../rtl/verilog/MAC_tx/MAC_tx_FF.v
-../../rtl/verilog/MAC_tx/Ramdon_gen.v
-
-../../rtl/verilog/miim/eth_clockgen.v
-../../rtl/verilog/miim/eth_outputcontrol.v
-../../rtl/verilog/miim/eth_shiftreg.v
-
-../../rtl/verilog/RMON/RMON_addr_gen.v
-../../rtl/verilog/RMON/RMON_ctrl.v
-../../rtl/verilog/RMON/RMON_dpram.v
-
-../../rtl/verilog/TECH/duram.v
-../../rtl/verilog/TECH/eth_clk_div2.v
-../../rtl/verilog/TECH/eth_clk_switch.v
-
-../../rtl/verilog/TECH/xilinx/BUFGMUX.v
-../../rtl/verilog/TECH/xilinx/RAMB16_S36_S36.v
-
-../../rtl/verilog/Clk_ctrl.v
-../../rtl/verilog/eth_miim.v
-../../rtl/verilog/MAC_rx.v
-../../rtl/verilog/MAC_top.v
-../../rtl/verilog/MAC_tx.v
-../../rtl/verilog/Phy_int.v
-../../rtl/verilog/Reg_int.v
-../../rtl/verilog/RMON.v
-
-../../bench/verilog/Phy_sim.v
-../../bench/verilog/User_int_sim.v
-../../bench/verilog/host_sim.v
-../../bench/verilog/xlnx_glbl.v
-../../bench/verilog/tb_top.v
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