diff options
| author | jcorgan <jcorgan@221aa14e-8319-0410-a670-987f0aec2ac5> | 2008-09-08 01:00:12 +0000 |
|---|---|---|
| committer | jcorgan <jcorgan@221aa14e-8319-0410-a670-987f0aec2ac5> | 2008-09-08 01:00:12 +0000 |
| commit | 61f2f0214c5999ea42a368a4fc99f03d8eb28d1e (patch) | |
| tree | e7e24a9adc05ff1422fe3ada9926a51634741b47 /coregen | |
| download | uhd-61f2f0214c5999ea42a368a4fc99f03d8eb28d1e.tar.gz uhd-61f2f0214c5999ea42a368a4fc99f03d8eb28d1e.tar.bz2 uhd-61f2f0214c5999ea42a368a4fc99f03d8eb28d1e.zip | |
Merged r9433:9527 from features/gr-usrp2 into trunk. Adds usrp2 and gr-usrp2 top-level components. Trunk passes distcheck with mb-gcc installed, but currently not without them. The key issue is that when mb-gcc is not installed, the build system skips over the usrp2/firmware directory, and the firmware include files don't get put into the dist tarball. But we can't do the usual DIST_SUBDIRS method as the firmware is a subpackage.
git-svn-id: http://gnuradio.org/svn/gnuradio/trunk@9528 221aa14e-8319-0410-a670-987f0aec2ac5
Diffstat (limited to 'coregen')
29 files changed, 2028 insertions, 0 deletions
diff --git a/coregen/coregen.cgp b/coregen/coregen.cgp new file mode 100644 index 000000000..1ee75a7b6 --- /dev/null +++ b/coregen/coregen.cgp @@ -0,0 +1,20 @@ +# Date: Mon Feb 4 20:12:22 2008 +SET addpads = False +SET asysymbol = False +SET busformat = BusFormatAngleBracketNotRipped +SET createndf = False +SET designentry = Verilog +SET device = xc3s1500 +SET devicefamily = spartan3 +SET flowvendor = Other +SET formalverification = False +SET foundationsym = False +SET implementationfiletype = Ngc +SET package = fg456 +SET removerpms = False +SET simulationfiles = Behavioral +SET speedgrade = -5 +SET verilogsim = True +SET vhdlsim = False +SET workingdirectory = /home/matt/coregen/tmp + diff --git a/coregen/fifo_generator_release_notes.txt b/coregen/fifo_generator_release_notes.txt new file mode 100644 index 000000000..554ec87f4 --- /dev/null +++ b/coregen/fifo_generator_release_notes.txt @@ -0,0 +1,160 @@ +COPYRIGHT (c) 2006, 2007 XILINX, INC. +ALL RIGHTS RESERVED + +Core name : FIFO Generator +Version : v4.1 +Release Date : August 8, 2007 +File : fifo_generator_release_notes.txt + +Revision History +Date By Version Change Description +======================================================================== +09/2006 Xilinx, Inc. 3.2 Initial creation. +02/2007 Xilinx, Inc. 3.3 Revised for v3.3. +02/2007 Xilinx, Inc. 3.3 Revised for v3.3 rev 1. +08/2007 Xilinx, Inc. 3.4 Revised for v4.1. +======================================================================== + +INTRODUCTION +RELEASE NOTES + 1. General Core Design + 1.1 Enhancements + 1.2 Resolved Issues + 1.3 Outstanding Issues + 2. General Simulation + 2.1 Enhancements + 2.2 Resolved Issues + 2.3 Outstanding Issues + 3. Documentation + 3.1 Enhancements + 3.2 Resolved Issues + 3.3 Outstanding Issues +OTHER GENERAL INFORMATION +TECHNICAL SUPPORT + +======================================================================== + +INTRODUCTION +============ +Thank you using the FIFO Generator core from Xilinx! +In order to obtain the latest core updates and documentation, +please visit the Intellectual Property page located at: +http://www.xilinx.com/ipcenter/index.htm +This document contains the release notes for FIFO Generator v4.1 +which includes enhancements, resolved issues and outstanding known +issues. For release notes and known issues for CORE Generator 9.2i IP +Update 1 and FIFO Generator v4.1 please see Answer Record 25222. + +RELEASE NOTES +============= +This section lists any enhancements, resolved issues and outstanding +known issues. + + +1. General Core Design + 1.1 Enhancements + 1.1.1 Error Correction Checking (ECC) feature support for + Virtex-5 block RAM FIFO configurations + + 1.1.2 Full range data count widths now supported for non-symmetric + aspect ratio configurations + + 1.1.3 Option to define asynchronous reset value for full condition + flags (FULL, ALMOST_FULL, PROG_FULL). Applies to block RAM, + distributed RAM and shift RAM-based FIFO configurations only + + 1.1.4 Support added for use embedded output registers in block RAM + FIFO configurations (Virtex-4 and Virtex-5 only) + + 1.2 Resolved Issues + 1.2.1 Coregen GUI - For built-in FIFOs, GUI reports incorrect + number of built-in FIFO primitives used. + Change request: 4433738 + + 1.2.2 Programmable full flag is always asserted even when FIFO is + empty due to incorrect threshold setting. + Change request: 435835 + + 1.2.3 "ERROR:LIT:250 - Pins WEA0, WEA1, WEA2, WEA3 of RAMB16 symbol + .. , these pins should be connected to the same signal" occur + during MAP when targeting Virtex-4 and Virtex-5. + Change request: 338260 + + 1.2.4 Write Data Count and Read Data Count overestimate the number + of words written or read when core is configured with this + combination of options: First-Word-Fall-Through(FWFT), + accurate data count using extra logic, non-symmetric port + aspect ratio. + Change request: 436886 + + 1.2.5 SBITERR and DBITERR outputs are not driven in behavior + models. + Change request: 433637 + + 1.2.6 Maximum programmable empty threshold negate value is + incorrect. + Change request: 433921 + + 1.2.7 Programmable full flag behavior is incorrect when the + core is configured with this combination of options: + FWFT, non-symmetric port aspect ratio, single or + multiple programmable full threshold input port. + Change request: 435874 + + 1.2.8 Programmable empty flag stuck high when the core is + configured with this combination of options: block or + distributed RAM FIFO, single or multiple programmable + empty threshold input port. + Change request: 443569 + + 1.3 Outstanding Issues + 1.3.1 "WARNING:Ngdbuild:452 - logical net + 'u1/BU2/prog_*_thresh_assert<*>' has no driver" occur during + NgdBuild although programmable empty or full is not selected. + Warnings can be safely ignored. + Change request: 431975 + +2. General Simulation + 2.1 Enhancements + None at this time. + + 2.2 Resolved Issues + None at this time. + + 2.3 Outstanding Issues + 2.3.1 Ncelab warnings during Verilog structural and timing simulations + in ncsim for Virtex5 Block RAM FIFOs. + The simulations will be successful, but there will be warnings + similar to the following in the log file: "memory index out of + declared bounds" in simprims_ver_virtex5_source.v or + unisims_ver_virtex5_source.v. Cadence does not want to fix this + issue. These warning messages can safely be ignored. + Change request: 423374, 423375 + +3. Documentation + 3.1 Enhancements + 3.1.1 Added clarification on FIFO flag latency. + + 3.1.1 Added clarification on actual FIFO depth. + + 3.2 Resolved Issues + None at this time. + + 3.3 Outstanding Issues + None at this time. + + +TECHNICAL SUPPORT +================= +The fastest method for obtaining specific technical support for the +FIFO Generator core is through the http://support.xilinx.com/ +website. Questions are routed to a team of engineers with specific +expertise in using the FIFO Generator core. Xilinx will provide +technical support for use of this product as described in the FIFO +Generator Datasheet. Xilinx cannot guarantee timing, functionality, +or support of this product for designs that do not follow these +guidelines. + + + + diff --git a/coregen/fifo_generator_ug175.pdf b/coregen/fifo_generator_ug175.pdf Binary files differnew file mode 100644 index 000000000..2c3e3c200 --- /dev/null +++ b/coregen/fifo_generator_ug175.pdf diff --git a/coregen/fifo_xlnx_2Kx36_2clk.asy b/coregen/fifo_xlnx_2Kx36_2clk.asy new file mode 100644 index 000000000..364ce6e1e --- /dev/null +++ b/coregen/fifo_xlnx_2Kx36_2clk.asy @@ -0,0 +1,49 @@ +Version 4 +SymbolType BLOCK +TEXT 32 32 LEFT 4 fifo_xlnx_2Kx36_2clk +RECTANGLE Normal 32 32 544 672 +LINE Wide 0 80 32 80 +PIN 0 80 LEFT 36 +PINATTR PinName din[35:0] +PINATTR Polarity IN +LINE Normal 0 144 32 144 +PIN 0 144 LEFT 36 +PINATTR PinName wr_en +PINATTR Polarity IN +LINE Normal 0 176 32 176 +PIN 0 176 LEFT 36 +PINATTR PinName wr_clk +PINATTR Polarity IN +LINE Normal 0 240 32 240 +PIN 0 240 LEFT 36 +PINATTR PinName rd_en +PINATTR Polarity IN +LINE Normal 0 272 32 272 +PIN 0 272 LEFT 36 +PINATTR PinName rd_clk +PINATTR Polarity IN +LINE Normal 144 704 144 672 +PIN 144 704 BOTTOM 36 +PINATTR PinName rst +PINATTR Polarity IN +LINE Wide 576 80 544 80 +PIN 576 80 RIGHT 36 +PINATTR PinName dout[35:0] +PINATTR Polarity OUT +LINE Normal 576 208 544 208 +PIN 576 208 RIGHT 36 +PINATTR PinName full +PINATTR Polarity OUT +LINE Wide 576 368 544 368 +PIN 576 368 RIGHT 36 +PINATTR PinName wr_data_count[10:0] +PINATTR Polarity OUT +LINE Normal 576 432 544 432 +PIN 576 432 RIGHT 36 +PINATTR PinName empty +PINATTR Polarity OUT +LINE Wide 576 592 544 592 +PIN 576 592 RIGHT 36 +PINATTR PinName rd_data_count[10:0] +PINATTR Polarity OUT + diff --git a/coregen/fifo_xlnx_2Kx36_2clk.ngc b/coregen/fifo_xlnx_2Kx36_2clk.ngc new file mode 100644 index 000000000..321f44d7d --- /dev/null +++ b/coregen/fifo_xlnx_2Kx36_2clk.ngc @@ -0,0 +1,3 @@ +XILINX-XDB 0.1 STUB 0.1 ASCII +XILINX-XDM V1.4e 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\ No newline at end of file diff --git a/coregen/fifo_xlnx_2Kx36_2clk.sym b/coregen/fifo_xlnx_2Kx36_2clk.sym new file mode 100644 index 000000000..ab6729a93 --- /dev/null +++ b/coregen/fifo_xlnx_2Kx36_2clk.sym @@ -0,0 +1,74 @@ +VERSION 5 +BEGIN SYMBOL fifo_xlnx_2Kx36_2clk +SYMBOLTYPE BLOCK +TIMESTAMP 2008 7 14 23 44 58 +SYMPIN 0 80 Input din[35:0] +SYMPIN 0 144 Input wr_en +SYMPIN 0 176 Input wr_clk +SYMPIN 0 240 Input rd_en +SYMPIN 0 272 Input rd_clk +SYMPIN 144 704 Input rst +SYMPIN 576 80 Output dout[35:0] +SYMPIN 576 208 Output full +SYMPIN 576 368 Output wr_data_count[10:0] +SYMPIN 576 432 Output empty +SYMPIN 576 592 Output rd_data_count[10:0] +BEGIN DISPLAY 32 32 TEXT fifo_xlnx_2Kx36_2clk + FONT 40 "Arial" +END DISPLAY +RECTANGLE N 32 32 544 672 +BEGIN LINE W 0 80 32 80 +END LINE +BEGIN DISPLAY 36 80 PIN din[35:0] ATTR PinName + FONT 24 "Arial" +END DISPLAY +LINE N 0 144 32 144 +BEGIN DISPLAY 36 144 PIN wr_en ATTR PinName + FONT 24 "Arial" +END DISPLAY +LINE N 0 176 32 176 +BEGIN DISPLAY 36 176 PIN wr_clk ATTR PinName + FONT 24 "Arial" +END DISPLAY +LINE N 0 240 32 240 +BEGIN DISPLAY 36 240 PIN rd_en ATTR PinName + FONT 24 "Arial" +END DISPLAY +LINE N 0 272 32 272 +BEGIN DISPLAY 36 272 PIN rd_clk ATTR PinName + FONT 24 "Arial" +END DISPLAY +LINE N 144 704 144 672 +BEGIN DISPLAY 144 668 PIN rst ATTR PinName + ALIGNMENT BCENTER + FONT 24 "Arial" +END DISPLAY +BEGIN LINE W 576 80 544 80 +END LINE +BEGIN DISPLAY 540 80 PIN dout[35:0] ATTR PinName + ALIGNMENT RIGHT + FONT 24 "Arial" +END DISPLAY +LINE N 576 208 544 208 +BEGIN DISPLAY 540 208 PIN full ATTR PinName + ALIGNMENT RIGHT + FONT 24 "Arial" +END DISPLAY +BEGIN LINE W 576 368 544 368 +END LINE +BEGIN DISPLAY 540 368 PIN wr_data_count[10:0] ATTR PinName + ALIGNMENT RIGHT + FONT 24 "Arial" +END DISPLAY +LINE N 576 432 544 432 +BEGIN DISPLAY 540 432 PIN empty ATTR PinName + ALIGNMENT RIGHT + FONT 24 "Arial" +END DISPLAY +BEGIN LINE W 576 592 544 592 +END LINE +BEGIN DISPLAY 540 592 PIN rd_data_count[10:0] ATTR PinName + ALIGNMENT RIGHT + FONT 24 "Arial" +END DISPLAY +END SYMBOL diff --git a/coregen/fifo_xlnx_2Kx36_2clk.v b/coregen/fifo_xlnx_2Kx36_2clk.v new file mode 100644 index 000000000..c45dacdad --- /dev/null +++ b/coregen/fifo_xlnx_2Kx36_2clk.v @@ -0,0 +1,173 @@ +/******************************************************************************* +* This file is owned and controlled by Xilinx and must be used * +* solely for design, simulation, implementation and creation of * +* design files limited to Xilinx devices or technologies. Use * +* with non-Xilinx devices or technologies is expressly prohibited * +* and immediately terminates your license. * +* * +* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" * +* SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR * +* XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION * +* AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION * +* OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS * +* IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, * +* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE * +* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY * +* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE * +* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR * +* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF * +* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS * +* FOR A PARTICULAR PURPOSE. * +* * +* Xilinx products are not intended for use in life support * +* appliances, devices, or systems. Use in such applications are * +* expressly prohibited. * +* * +* (c) Copyright 1995-2007 Xilinx, Inc. * +* All rights reserved. * +*******************************************************************************/ +// The synthesis directives "translate_off/translate_on" specified below are +// supported by Xilinx, Mentor Graphics and Synplicity synthesis +// tools. Ensure they are correct for your synthesis tool(s). + +// You must compile the wrapper file fifo_xlnx_2Kx36_2clk.v when simulating +// the core, fifo_xlnx_2Kx36_2clk. When compiling the wrapper file, be sure to +// reference the XilinxCoreLib Verilog simulation library. For detailed +// instructions, please refer to the "CORE Generator Help". + +`timescale 1ns/1ps + +module fifo_xlnx_2Kx36_2clk( + din, + rd_clk, + rd_en, + rst, + wr_clk, + wr_en, + dout, + empty, + full, + rd_data_count, + wr_data_count); + + +input [35 : 0] din; +input rd_clk; +input rd_en; +input rst; +input wr_clk; +input wr_en; +output [35 : 0] dout; +output empty; +output full; +output [10 : 0] rd_data_count; +output [10 : 0] wr_data_count; + +// synthesis translate_off + + FIFO_GENERATOR_V4_3 #( + .C_COMMON_CLOCK(0), + .C_COUNT_TYPE(0), + .C_DATA_COUNT_WIDTH(11), + .C_DEFAULT_VALUE("BlankString"), + .C_DIN_WIDTH(36), + .C_DOUT_RST_VAL("0"), + .C_DOUT_WIDTH(36), + .C_ENABLE_RLOCS(0), + .C_FAMILY("spartan3"), + .C_FULL_FLAGS_RST_VAL(1), + .C_HAS_ALMOST_EMPTY(0), + .C_HAS_ALMOST_FULL(0), + .C_HAS_BACKUP(0), + .C_HAS_DATA_COUNT(0), + .C_HAS_INT_CLK(0), + .C_HAS_MEMINIT_FILE(0), + .C_HAS_OVERFLOW(0), + .C_HAS_RD_DATA_COUNT(1), + .C_HAS_RD_RST(0), + .C_HAS_RST(1), + .C_HAS_SRST(0), + .C_HAS_UNDERFLOW(0), + .C_HAS_VALID(0), + .C_HAS_WR_ACK(0), + .C_HAS_WR_DATA_COUNT(1), + .C_HAS_WR_RST(0), + .C_IMPLEMENTATION_TYPE(2), + .C_INIT_WR_PNTR_VAL(0), + .C_MEMORY_TYPE(1), + .C_MIF_FILE_NAME("BlankString"), + .C_MSGON_VAL(1), + .C_OPTIMIZATION_MODE(0), + .C_OVERFLOW_LOW(0), + .C_PRELOAD_LATENCY(0), + .C_PRELOAD_REGS(1), + .C_PRIM_FIFO_TYPE("2kx18"), + .C_PROG_EMPTY_THRESH_ASSERT_VAL(4), + .C_PROG_EMPTY_THRESH_NEGATE_VAL(5), + .C_PROG_EMPTY_TYPE(0), + .C_PROG_FULL_THRESH_ASSERT_VAL(2047), + .C_PROG_FULL_THRESH_NEGATE_VAL(2046), + .C_PROG_FULL_TYPE(0), + .C_RD_DATA_COUNT_WIDTH(11), + .C_RD_DEPTH(2048), + .C_RD_FREQ(1), + .C_RD_PNTR_WIDTH(11), + .C_UNDERFLOW_LOW(0), + .C_USE_DOUT_RST(0), + .C_USE_ECC(0), + .C_USE_EMBEDDED_REG(0), + .C_USE_FIFO16_FLAGS(0), + .C_USE_FWFT_DATA_COUNT(0), + .C_VALID_LOW(0), + .C_WR_ACK_LOW(0), + .C_WR_DATA_COUNT_WIDTH(11), + .C_WR_DEPTH(2048), + .C_WR_FREQ(1), + .C_WR_PNTR_WIDTH(11), + .C_WR_RESPONSE_LATENCY(1)) + inst ( + .DIN(din), + .RD_CLK(rd_clk), + .RD_EN(rd_en), + .RST(rst), + .WR_CLK(wr_clk), + .WR_EN(wr_en), + .DOUT(dout), + .EMPTY(empty), + .FULL(full), + .RD_DATA_COUNT(rd_data_count), + .WR_DATA_COUNT(wr_data_count), + .CLK(), + .INT_CLK(), + .BACKUP(), + .BACKUP_MARKER(), + .PROG_EMPTY_THRESH(), + .PROG_EMPTY_THRESH_ASSERT(), + .PROG_EMPTY_THRESH_NEGATE(), + .PROG_FULL_THRESH(), + .PROG_FULL_THRESH_ASSERT(), + .PROG_FULL_THRESH_NEGATE(), + .RD_RST(), + .SRST(), + .WR_RST(), + .ALMOST_EMPTY(), + .ALMOST_FULL(), + .DATA_COUNT(), + .OVERFLOW(), + .PROG_EMPTY(), + .PROG_FULL(), + .VALID(), + .UNDERFLOW(), + .WR_ACK(), + .SBITERR(), + .DBITERR()); + + +// synthesis translate_on + +// XST black box declaration +// box_type "black_box" +// synthesis attribute box_type of fifo_xlnx_2Kx36_2clk is "black_box" + +endmodule + diff --git a/coregen/fifo_xlnx_2Kx36_2clk.veo b/coregen/fifo_xlnx_2Kx36_2clk.veo new file mode 100644 index 000000000..bb691ff4d --- /dev/null +++ b/coregen/fifo_xlnx_2Kx36_2clk.veo @@ -0,0 +1,53 @@ +/******************************************************************************* +* This file is owned and controlled by Xilinx and must be used * +* solely for design, simulation, implementation and creation of * +* design files limited to Xilinx devices or technologies. Use * +* with non-Xilinx devices or technologies is expressly prohibited * +* and immediately terminates your license. * +* * +* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" * +* SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR * +* XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION * +* AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION * +* OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS * +* IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, * +* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE * +* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY * +* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE * +* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR * +* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF * +* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS * +* FOR A PARTICULAR PURPOSE. * +* * +* Xilinx products are not intended for use in life support * +* appliances, devices, or systems. Use in such applications are * +* expressly prohibited. * +* * +* (c) Copyright 1995-2007 Xilinx, Inc. * +* All rights reserved. * +*******************************************************************************/ +// The following must be inserted into your Verilog file for this +// core to be instantiated. Change the instance name and port connections +// (in parentheses) to your own signal names. + +//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG +fifo_xlnx_2Kx36_2clk YourInstanceName ( + .din(din), // Bus [35 : 0] + .rd_clk(rd_clk), + .rd_en(rd_en), + .rst(rst), + .wr_clk(wr_clk), + .wr_en(wr_en), + .dout(dout), // Bus [35 : 0] + .empty(empty), + .full(full), + .rd_data_count(rd_data_count), // Bus [10 : 0] + .wr_data_count(wr_data_count)); // Bus [10 : 0] + +// INST_TAG_END ------ End INSTANTIATION Template --------- + +// You must compile the wrapper file fifo_xlnx_2Kx36_2clk.v when simulating +// the core, fifo_xlnx_2Kx36_2clk. When compiling the wrapper file, be sure to +// reference the XilinxCoreLib Verilog simulation library. For detailed +// instructions, please refer to the "CORE Generator Help". + diff --git a/coregen/fifo_xlnx_2Kx36_2clk.vhd b/coregen/fifo_xlnx_2Kx36_2clk.vhd new file mode 100644 index 000000000..834abf271 --- /dev/null +++ b/coregen/fifo_xlnx_2Kx36_2clk.vhd @@ -0,0 +1,156 @@ +-------------------------------------------------------------------------------- +-- This file is owned and controlled by Xilinx and must be used -- +-- solely for design, simulation, implementation and creation of -- +-- design files limited to Xilinx devices or technologies. Use -- +-- with non-Xilinx devices or technologies is expressly prohibited -- +-- and immediately terminates your license. -- +-- -- +-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" -- +-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR -- +-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION -- +-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION -- +-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS -- +-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, -- +-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE -- +-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY -- +-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE -- +-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR -- +-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF -- +-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -- +-- FOR A PARTICULAR PURPOSE. -- +-- -- +-- Xilinx products are not intended for use in life support -- +-- appliances, devices, or systems. Use in such applications are -- +-- expressly prohibited. -- +-- -- +-- (c) Copyright 1995-2007 Xilinx, Inc. -- +-- All rights reserved. -- +-------------------------------------------------------------------------------- +-- You must compile the wrapper file fifo_xlnx_2Kx36_2clk.vhd when simulating +-- the core, fifo_xlnx_2Kx36_2clk. When compiling the wrapper file, be sure to +-- reference the XilinxCoreLib VHDL simulation library. For detailed +-- instructions, please refer to the "CORE Generator Help". + +-- The synthesis directives "translate_off/translate_on" specified +-- below are supported by Xilinx, Mentor Graphics and Synplicity +-- synthesis tools. Ensure they are correct for your synthesis tool(s). + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +-- synthesis translate_off +Library XilinxCoreLib; +-- synthesis translate_on +ENTITY fifo_xlnx_2Kx36_2clk IS + port ( + din: IN std_logic_VECTOR(35 downto 0); + rd_clk: IN std_logic; + rd_en: IN std_logic; + rst: IN std_logic; + wr_clk: IN std_logic; + wr_en: IN std_logic; + dout: OUT std_logic_VECTOR(35 downto 0); + empty: OUT std_logic; + full: OUT std_logic; + rd_data_count: OUT std_logic_VECTOR(10 downto 0); + wr_data_count: OUT std_logic_VECTOR(10 downto 0)); +END fifo_xlnx_2Kx36_2clk; + +ARCHITECTURE fifo_xlnx_2Kx36_2clk_a OF fifo_xlnx_2Kx36_2clk IS +-- synthesis translate_off +component wrapped_fifo_xlnx_2Kx36_2clk + port ( + din: IN std_logic_VECTOR(35 downto 0); + rd_clk: IN std_logic; + rd_en: IN std_logic; + rst: IN std_logic; + wr_clk: IN std_logic; + wr_en: IN std_logic; + dout: OUT std_logic_VECTOR(35 downto 0); + empty: OUT std_logic; + full: OUT std_logic; + rd_data_count: OUT std_logic_VECTOR(10 downto 0); + wr_data_count: OUT std_logic_VECTOR(10 downto 0)); +end component; + +-- Configuration specification + for all : wrapped_fifo_xlnx_2Kx36_2clk use entity XilinxCoreLib.fifo_generator_v4_3(behavioral) + generic map( + c_has_int_clk => 0, + c_rd_freq => 1, + c_wr_response_latency => 1, + c_has_srst => 0, + c_has_rd_data_count => 1, + c_din_width => 36, + c_has_wr_data_count => 1, + c_full_flags_rst_val => 1, + c_implementation_type => 2, + c_family => "spartan3", + c_use_embedded_reg => 0, + c_has_wr_rst => 0, + c_wr_freq => 1, + c_use_dout_rst => 0, + c_underflow_low => 0, + c_has_meminit_file => 0, + c_has_overflow => 0, + c_preload_latency => 0, + c_dout_width => 36, + c_msgon_val => 1, + c_rd_depth => 2048, + c_default_value => "BlankString", + c_mif_file_name => "BlankString", + c_has_underflow => 0, + c_has_rd_rst => 0, + c_has_almost_full => 0, + c_has_rst => 1, + c_data_count_width => 11, + c_has_wr_ack => 0, + c_use_ecc => 0, + c_wr_ack_low => 0, + c_common_clock => 0, + c_rd_pntr_width => 11, + c_use_fwft_data_count => 0, + c_has_almost_empty => 0, + c_rd_data_count_width => 11, + c_enable_rlocs => 0, + c_wr_pntr_width => 11, + c_overflow_low => 0, + c_prog_empty_type => 0, + c_optimization_mode => 0, + c_wr_data_count_width => 11, + c_preload_regs => 1, + c_dout_rst_val => "0", + c_has_data_count => 0, + c_prog_full_thresh_negate_val => 2046, + c_wr_depth => 2048, + c_prog_empty_thresh_negate_val => 5, + c_prog_empty_thresh_assert_val => 4, + c_has_valid => 0, + c_init_wr_pntr_val => 0, + c_prog_full_thresh_assert_val => 2047, + c_use_fifo16_flags => 0, + c_has_backup => 0, + c_valid_low => 0, + c_prim_fifo_type => "2kx18", + c_count_type => 0, + c_prog_full_type => 0, + c_memory_type => 1); +-- synthesis translate_on +BEGIN +-- synthesis translate_off +U0 : wrapped_fifo_xlnx_2Kx36_2clk + port map ( + din => din, + rd_clk => rd_clk, + rd_en => rd_en, + rst => rst, + wr_clk => wr_clk, + wr_en => wr_en, + dout => dout, + empty => empty, + full => full, + rd_data_count => rd_data_count, + wr_data_count => wr_data_count); +-- synthesis translate_on + +END fifo_xlnx_2Kx36_2clk_a; + diff --git a/coregen/fifo_xlnx_2Kx36_2clk.vho b/coregen/fifo_xlnx_2Kx36_2clk.vho new file mode 100644 index 000000000..3fd2e43f1 --- /dev/null +++ b/coregen/fifo_xlnx_2Kx36_2clk.vho @@ -0,0 +1,76 @@ +-------------------------------------------------------------------------------- +-- This file is owned and controlled by Xilinx and must be used -- +-- solely for design, simulation, implementation and creation of -- +-- design files limited to Xilinx devices or technologies. Use -- +-- with non-Xilinx devices or technologies is expressly prohibited -- +-- and immediately terminates your license. -- +-- -- +-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" -- +-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR -- +-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION -- +-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION -- +-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS -- +-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, -- +-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE -- +-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY -- +-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE -- +-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR -- +-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF -- +-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -- +-- FOR A PARTICULAR PURPOSE. -- +-- -- +-- Xilinx products are not intended for use in life support -- +-- appliances, devices, or systems. Use in such applications are -- +-- expressly prohibited. -- +-- -- +-- (c) Copyright 1995-2007 Xilinx, Inc. -- +-- All rights reserved. -- +-------------------------------------------------------------------------------- +-- The following code must appear in the VHDL architecture header: + +------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG +component fifo_xlnx_2Kx36_2clk + port ( + din: IN std_logic_VECTOR(35 downto 0); + rd_clk: IN std_logic; + rd_en: IN std_logic; + rst: IN std_logic; + wr_clk: IN std_logic; + wr_en: IN std_logic; + dout: OUT std_logic_VECTOR(35 downto 0); + empty: OUT std_logic; + full: OUT std_logic; + rd_data_count: OUT std_logic_VECTOR(10 downto 0); + wr_data_count: OUT std_logic_VECTOR(10 downto 0)); +end component; + +-- Synplicity black box declaration +attribute syn_black_box : boolean; +attribute syn_black_box of fifo_xlnx_2Kx36_2clk: component is true; + +-- COMP_TAG_END ------ End COMPONENT Declaration ------------ + +-- The following code must appear in the VHDL architecture +-- body. Substitute your own instance name and net names. + +------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG +your_instance_name : fifo_xlnx_2Kx36_2clk + port map ( + din => din, + rd_clk => rd_clk, + rd_en => rd_en, + rst => rst, + wr_clk => wr_clk, + wr_en => wr_en, + dout => dout, + empty => empty, + full => full, + rd_data_count => rd_data_count, + wr_data_count => wr_data_count); +-- INST_TAG_END ------ End INSTANTIATION Template ------------ + +-- You must compile the wrapper file fifo_xlnx_2Kx36_2clk.vhd when simulating +-- the core, fifo_xlnx_2Kx36_2clk. When compiling the wrapper file, be sure to +-- reference the XilinxCoreLib VHDL simulation library. For detailed +-- instructions, please refer to the "CORE Generator Help". + diff --git a/coregen/fifo_xlnx_2Kx36_2clk.xco b/coregen/fifo_xlnx_2Kx36_2clk.xco new file mode 100644 index 000000000..3afc64a10 --- /dev/null +++ b/coregen/fifo_xlnx_2Kx36_2clk.xco @@ -0,0 +1,82 @@ +############################################################## +# +# Xilinx Core Generator version K.37 +# Date: Mon Jul 14 23:45:29 2008 +# +############################################################## +# +# This file contains the customisation parameters for a +# Xilinx CORE Generator IP GUI. It is strongly recommended +# that you do not manually alter this file as it may cause +# unexpected and unsupported behavior. +# +############################################################## +# +# BEGIN Project Options +SET addpads = False +SET asysymbol = True +SET busformat = BusFormatAngleBracketNotRipped +SET createndf = False +SET designentry = VHDL +SET device = xc3s2000 +SET devicefamily = spartan3 +SET flowvendor = Foundation_iSE +SET formalverification = False +SET foundationsym = False +SET implementationfiletype = Ngc +SET package = fg456 +SET removerpms = False +SET simulationfiles = Behavioral +SET speedgrade = -5 +SET verilogsim = True +SET vhdlsim = True +# END Project Options +# BEGIN Select +SELECT Fifo_Generator family Xilinx,_Inc. 4.3 +# END Select +# BEGIN Parameters +CSET almost_empty_flag=false +CSET almost_full_flag=false +CSET component_name=fifo_xlnx_2Kx36_2clk +CSET data_count=false +CSET data_count_width=11 +CSET disable_timing_violations=false +CSET dout_reset_value=0 +CSET empty_threshold_assert_value=4 +CSET empty_threshold_negate_value=5 +CSET enable_ecc=false +CSET enable_int_clk=false +CSET fifo_implementation=Independent_Clocks_Block_RAM +CSET full_flags_reset_value=1 +CSET full_threshold_assert_value=2047 +CSET full_threshold_negate_value=2046 +CSET input_data_width=36 +CSET input_depth=2048 +CSET output_data_width=36 +CSET output_depth=2048 +CSET overflow_flag=false +CSET overflow_sense=Active_High +CSET performance_options=First_Word_Fall_Through +CSET programmable_empty_type=No_Programmable_Empty_Threshold +CSET programmable_full_type=No_Programmable_Full_Threshold +CSET read_clock_frequency=1 +CSET read_data_count=true +CSET read_data_count_width=11 +CSET reset_pin=true +CSET reset_type=Asynchronous_Reset +CSET underflow_flag=false +CSET underflow_sense=Active_High +CSET use_dout_reset=false +CSET use_embedded_registers=false +CSET use_extra_logic=false +CSET valid_flag=false +CSET valid_sense=Active_High +CSET write_acknowledge_flag=false +CSET write_acknowledge_sense=Active_High +CSET write_clock_frequency=1 +CSET write_data_count=true +CSET write_data_count_width=11 +# END Parameters +GENERATE +# CRC: a8b698f5 + diff --git a/coregen/fifo_xlnx_2Kx36_2clk_fifo_generator_v4_3_xst_1.lso b/coregen/fifo_xlnx_2Kx36_2clk_fifo_generator_v4_3_xst_1.lso new file mode 100644 index 000000000..f1a6f7899 --- /dev/null +++ b/coregen/fifo_xlnx_2Kx36_2clk_fifo_generator_v4_3_xst_1.lso @@ -0,0 +1,3 @@ +blkmemdp_v6_2 +blk_mem_gen_v2_6 +fifo_generator_v4_3 diff --git a/coregen/fifo_xlnx_2Kx36_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt b/coregen/fifo_xlnx_2Kx36_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt new file mode 100644 index 000000000..7089f8c2d --- /dev/null +++ b/coregen/fifo_xlnx_2Kx36_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt @@ -0,0 +1,105 @@ +<?xml version="1.0" encoding="UTF-8" standalone="yes" ?> +<document OS="lin64" product="ISE" version="10.1.02"> + + <!--The data in this file is primarily intended for consumption by Xilinx tools. + The structure and the elements are likely to change over the next few releases. + This means code written to parse this file will need to be revisited each subsequent release.--> + + <application stringID="Xst" timeStamp="Mon Jul 14 16:45:03 2008"> + <section stringID="XST_HDL_SYNTHESIS_REPORT"> + <item dataType="int" stringID="XST_ADDERSSUBTRACTORS" value="2"></item> + <item dataType="int" stringID="XST_COUNTERS" value="2"> + <item dataType="int" stringID="XST_11BIT_UP_COUNTER" value="2"/> + </item> + <item dataType="int" stringID="XST_REGISTERS" value="31"> + <item dataType="int" stringID="XST_1BIT_REGISTER" value="15"/> + <item dataType="int" stringID="XST_11BIT_REGISTER" value="13"/> + <item dataType="int" stringID="XST_2BIT_REGISTER" value="1"/> + <item dataType="int" stringID="XST_3BIT_REGISTER" value="1"/> + <item dataType="int" stringID="XST_36BIT_REGISTER" value="1"/> + </item> + <item dataType="int" stringID="XST_XORS" value="91"> + <item dataType="int" stringID="XST_1BIT_XOR2" value="90"/> + <item dataType="int" stringID="XST_1BIT_XOR6" value="1"/> + </item> + </section> + <section stringID="XST_ADVANCED_HDL_SYNTHESIS_REPORT"> + <item dataType="int" stringID="XST_FSMS" value="1"/> + <item dataType="int" stringID="XST_ADDERSSUBTRACTORS" value="2"></item> + <item dataType="int" stringID="XST_COUNTERS" value="2"> + <item dataType="int" stringID="XST_11BIT_UP_COUNTER" value="2"/> + </item> + <item dataType="int" stringID="XST_REGISTERS" value="199"> + <item dataType="int" stringID="XST_FLIPFLOPS" value="199"/> + </item> + <item dataType="int" stringID="XST_XORS" value="91"> + <item dataType="int" stringID="XST_1BIT_XOR2" value="90"/> + <item dataType="int" stringID="XST_1BIT_XOR6" value="1"/> + </item> + </section> + <section stringID="XST_FINAL_REGISTER_REPORT"> + <item dataType="int" stringID="XST_REGISTERS" value="218"> + <item dataType="int" stringID="XST_FLIPFLOPS" value="218"/> + </item> + </section> + <section stringID="XST_PARTITION_REPORT"> + <section stringID="XST_PARTITION_IMPLEMENTATION_STATUS"> + <section stringID="XST_NO_PARTITIONS_WERE_FOUND_IN_THIS_DESIGN"/> + </section> + </section> + <section stringID="XST_FINAL_REPORT"> + <section stringID="XST_FINAL_RESULTS"> + <item stringID="XST_TOP_LEVEL_OUTPUT_FILE_NAME" value="tmp/_cg/fifo_xlnx_2Kx36_2clk_fifo_generator_v4_3_xst_1.ngc"/> + <item stringID="XST_OUTPUT_FORMAT" value="NGC"/> + <item stringID="XST_OPTIMIZATION_GOAL" value="SPEED"/> + <item stringID="XST_KEEP_HIERARCHY" value="no"/> + </section> + <section stringID="XST_DESIGN_STATISTICS"> + <item stringID="XST_IOS" value="195"/> + </section> + <section stringID="XST_CELL_USAGE"> + <item dataType="int" stringID="XST_BELS" value="234"> + <item dataType="int" stringID="XST_GND" value="1"/> + <item dataType="int" stringID="XST_LUT1" value="22"/> + <item dataType="int" stringID="XST_LUT2" value="55"/> + <item dataType="int" stringID="XST_LUT2L" value="1"/> + <item dataType="int" stringID="XST_LUT3" value="11"/> + <item dataType="int" stringID="XST_LUT4" value="33"/> + <item dataType="int" stringID="XST_LUT4L" value="2"/> + <item dataType="int" stringID="XST_MUXCY" value="64"/> + <item dataType="int" stringID="XST_VCC" value="1"/> + <item dataType="int" stringID="XST_XORCY" value="44"/> + </item> + <item dataType="int" stringID="XST_FLIPFLOPSLATCHES" value="218"> + <item dataType="int" stringID="XST_FD" value="4"/> + <item dataType="int" stringID="XST_FDC" value="112"/> + <item dataType="int" stringID="XST_FDCE" value="52"/> + <item dataType="int" stringID="XST_FDE" value="36"/> + <item dataType="int" stringID="XST_FDP" value="9"/> + <item dataType="int" stringID="XST_FDPE" value="5"/> + </item> + <item dataType="int" stringID="XST_RAMS" value="4"> + <item dataType="int" stringID="XST_RAMB16S9S9" value="4"/> + </item> + </section> + </section> + <section stringID="XST_DEVICE_UTILIZATION_SUMMARY"> + <item stringID="XST_SELECTED_DEVICE" value="3s2000fg456-5"/> + <item AVAILABLE="20480" dataType="int" stringID="XST_NUMBER_OF_SLICES" value="138"/> + <item AVAILABLE="40960" dataType="int" stringID="XST_NUMBER_OF_SLICE_FLIP_FLOPS" value="218"/> + <item AVAILABLE="40960" dataType="int" stringID="XST_NUMBER_OF_4_INPUT_LUTS" value="124"/> + <item dataType="int" stringID="XST_NUMBER_OF_IOS" value="195"/> + <item AVAILABLE="333" dataType="int" stringID="XST_NUMBER_OF_BONDED_IOBS" value="0"/> + <item AVAILABLE="40" dataType="int" stringID="XST_NUMBER_OF_BRAMS" value="4"/> + </section> + <section stringID="XST_PARTITION_RESOURCE_SUMMARY"> + <section stringID="XST_NO_PARTITIONS_WERE_FOUND_IN_THIS_DESIGN"/> + </section> + <section stringID="XST_ERRORS_STATISTICS"> + <item dataType="int" filtered="0" stringID="XST_NUMBER_OF_ERRORS" value="0"/> + <item dataType="int" filtered="0" stringID="XST_NUMBER_OF_WARNINGS" value="199"/> + <item dataType="int" filtered="0" stringID="XST_NUMBER_OF_INFOS" value="28"/> + </section> + </application> + +</document> diff --git a/coregen/fifo_xlnx_2Kx36_2clk_flist.txt b/coregen/fifo_xlnx_2Kx36_2clk_flist.txt new file mode 100644 index 000000000..670d84713 --- /dev/null +++ b/coregen/fifo_xlnx_2Kx36_2clk_flist.txt @@ -0,0 +1,12 @@ +# Output products list for <fifo_xlnx_2Kx36_2clk> +fifo_xlnx_2Kx36_2clk.asy +fifo_xlnx_2Kx36_2clk.ngc +fifo_xlnx_2Kx36_2clk.sym +fifo_xlnx_2Kx36_2clk.v +fifo_xlnx_2Kx36_2clk.veo +fifo_xlnx_2Kx36_2clk.vhd +fifo_xlnx_2Kx36_2clk.vho +fifo_xlnx_2Kx36_2clk.xco +fifo_xlnx_2Kx36_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt +fifo_xlnx_2Kx36_2clk_flist.txt +fifo_xlnx_2Kx36_2clk_xmdf.tcl diff --git a/coregen/fifo_xlnx_2Kx36_2clk_readme.txt b/coregen/fifo_xlnx_2Kx36_2clk_readme.txt new file mode 100644 index 000000000..86b8f03e1 --- /dev/null +++ b/coregen/fifo_xlnx_2Kx36_2clk_readme.txt @@ -0,0 +1,55 @@ +The following files were generated for 'fifo_xlnx_2Kx36_2clk' in directory +/home/matt/usrp2/fpga/coregen: + +fifo_xlnx_2Kx36_2clk.asy: + Graphical symbol information file. Used by the ISE tools and some + third party tools to create a symbol representing the core. + +fifo_xlnx_2Kx36_2clk.ngc: + Binary Xilinx implementation netlist file containing the information + required to implement the module in a Xilinx (R) FPGA. + +fifo_xlnx_2Kx36_2clk.sym: + Please see the core data sheet. + +fifo_xlnx_2Kx36_2clk.v: + Verilog wrapper file provided to support functional simulation. + This file contains simulation model customization data that is + passed to a parameterized simulation model for the core. + +fifo_xlnx_2Kx36_2clk.veo: + VEO template file containing code that can be used as a model for + instantiating a CORE Generator module in a Verilog design. + +fifo_xlnx_2Kx36_2clk.vhd: + VHDL wrapper file provided to support functional simulation. This + file contains simulation model customization data that is passed to + a parameterized simulation model for the core. + +fifo_xlnx_2Kx36_2clk.vho: + VHO template file containing code that can be used as a model for + instantiating a CORE Generator module in a VHDL design. + +fifo_xlnx_2Kx36_2clk.xco: + CORE Generator input file containing the parameters used to + regenerate a core. + +fifo_xlnx_2Kx36_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt: + Please see the core data sheet. + +fifo_xlnx_2Kx36_2clk_flist.txt: + Text file listing all of the output files produced when a customized + core was generated in the CORE Generator. + +fifo_xlnx_2Kx36_2clk_readme.txt: + Text file indicating the files generated and how they are used. + +fifo_xlnx_2Kx36_2clk_xmdf.tcl: + ISE Project Navigator interface file. ISE uses this file to determine + how the files output by CORE Generator for the core can be integrated + into your ISE project. + + +Please see the Xilinx CORE Generator online help for further details on +generated files and how to use them. + diff --git a/coregen/fifo_xlnx_2Kx36_2clk_xmdf.tcl b/coregen/fifo_xlnx_2Kx36_2clk_xmdf.tcl new file mode 100644 index 000000000..cac25efd2 --- /dev/null +++ b/coregen/fifo_xlnx_2Kx36_2clk_xmdf.tcl @@ -0,0 +1,84 @@ +# The package naming convention is <core_name>_xmdf +package provide fifo_xlnx_2Kx36_2clk_xmdf 1.0 + +# This includes some utilities that support common XMDF operations +package require utilities_xmdf + +# Define a namespace for this package. The name of the name space +# is <core_name>_xmdf +namespace eval ::fifo_xlnx_2Kx36_2clk_xmdf { +# Use this to define any statics +} + +# Function called by client to rebuild the params and port arrays +# Optional when the use context does not require the param or ports +# arrays to be available. +proc ::fifo_xlnx_2Kx36_2clk_xmdf::xmdfInit { instance } { +# Variable containg name of library into which module is compiled +# Recommendation: <module_name> +# Required +utilities_xmdf::xmdfSetData $instance Module Attributes Name fifo_xlnx_2Kx36_2clk +} +# ::fifo_xlnx_2Kx36_2clk_xmdf::xmdfInit + +# Function called by client to fill in all the xmdf* data variables +# based on the current settings of the parameters +proc ::fifo_xlnx_2Kx36_2clk_xmdf::xmdfApplyParams { instance } { + +set fcount 0 +# Array containing libraries that are assumed to exist +# Examples include unisim and xilinxcorelib +# Optional +# In this example, we assume that the unisim library will +# be magically +# available to the simulation and synthesis tool +utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library +utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_2Kx36_2clk.asy +utilities_xmdf::xmdfSetData $instance FileSet $fcount type asy +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_2Kx36_2clk.ngc +utilities_xmdf::xmdfSetData $instance FileSet $fcount type ngc +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_2Kx36_2clk.sym +utilities_xmdf::xmdfSetData $instance FileSet $fcount type symbol +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_2Kx36_2clk.v +utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_2Kx36_2clk.veo +utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog_template +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_2Kx36_2clk.vhd +utilities_xmdf::xmdfSetData $instance FileSet $fcount type vhdl +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_2Kx36_2clk.vho +utilities_xmdf::xmdfSetData $instance FileSet $fcount type vhdl_template +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_2Kx36_2clk.xco +utilities_xmdf::xmdfSetData $instance FileSet $fcount type coregen_ip +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_2Kx36_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt +utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_2Kx36_2clk_xmdf.tcl +utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module fifo_xlnx_2Kx36_2clk +incr fcount + +} + +# ::gen_comp_name_xmdf::xmdfApplyParams diff --git a/coregen/fifo_xlnx_512x36_2clk.asy b/coregen/fifo_xlnx_512x36_2clk.asy new file mode 100644 index 000000000..ecc80b648 --- /dev/null +++ b/coregen/fifo_xlnx_512x36_2clk.asy @@ -0,0 +1,49 @@ +Version 4 +SymbolType BLOCK +TEXT 32 32 LEFT 4 fifo_xlnx_512x36_2clk +RECTANGLE Normal 32 32 544 672 +LINE Wide 0 80 32 80 +PIN 0 80 LEFT 36 +PINATTR PinName din[35:0] +PINATTR Polarity IN +LINE Normal 0 144 32 144 +PIN 0 144 LEFT 36 +PINATTR PinName wr_en +PINATTR Polarity IN +LINE Normal 0 176 32 176 +PIN 0 176 LEFT 36 +PINATTR PinName wr_clk +PINATTR Polarity IN +LINE Normal 0 240 32 240 +PIN 0 240 LEFT 36 +PINATTR PinName rd_en +PINATTR Polarity IN +LINE Normal 0 272 32 272 +PIN 0 272 LEFT 36 +PINATTR PinName rd_clk +PINATTR Polarity IN +LINE Normal 144 704 144 672 +PIN 144 704 BOTTOM 36 +PINATTR PinName rst +PINATTR Polarity IN +LINE Wide 576 80 544 80 +PIN 576 80 RIGHT 36 +PINATTR PinName dout[35:0] +PINATTR Polarity OUT +LINE Normal 576 208 544 208 +PIN 576 208 RIGHT 36 +PINATTR PinName full +PINATTR Polarity OUT +LINE Wide 576 368 544 368 +PIN 576 368 RIGHT 36 +PINATTR PinName wr_data_count[8:0] +PINATTR Polarity OUT +LINE Normal 576 432 544 432 +PIN 576 432 RIGHT 36 +PINATTR PinName empty +PINATTR Polarity OUT +LINE Wide 576 592 544 592 +PIN 576 592 RIGHT 36 +PINATTR PinName rd_data_count[8:0] +PINATTR Polarity OUT + diff --git a/coregen/fifo_xlnx_512x36_2clk.ngc b/coregen/fifo_xlnx_512x36_2clk.ngc new file mode 100644 index 000000000..618ccf766 --- /dev/null +++ b/coregen/fifo_xlnx_512x36_2clk.ngc @@ -0,0 +1,3 @@ +XILINX-XDB 0.1 STUB 0.1 ASCII +XILINX-XDM V1.4e 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\ No newline at end of file diff --git a/coregen/fifo_xlnx_512x36_2clk.sym b/coregen/fifo_xlnx_512x36_2clk.sym new file mode 100644 index 000000000..13e8af33d --- /dev/null +++ b/coregen/fifo_xlnx_512x36_2clk.sym @@ -0,0 +1,74 @@ +VERSION 5 +BEGIN SYMBOL fifo_xlnx_512x36_2clk +SYMBOLTYPE BLOCK +TIMESTAMP 2008 7 28 22 45 53 +SYMPIN 0 80 Input din[35:0] +SYMPIN 0 144 Input wr_en +SYMPIN 0 176 Input wr_clk +SYMPIN 0 240 Input rd_en +SYMPIN 0 272 Input rd_clk +SYMPIN 144 704 Input rst +SYMPIN 576 80 Output dout[35:0] +SYMPIN 576 208 Output full +SYMPIN 576 368 Output wr_data_count[8:0] +SYMPIN 576 432 Output empty +SYMPIN 576 592 Output rd_data_count[8:0] +BEGIN DISPLAY 32 32 TEXT fifo_xlnx_512x36_2clk + FONT 40 "Arial" +END DISPLAY +RECTANGLE N 32 32 544 672 +BEGIN LINE W 0 80 32 80 +END LINE +BEGIN DISPLAY 36 80 PIN din[35:0] ATTR PinName + FONT 24 "Arial" +END DISPLAY +LINE N 0 144 32 144 +BEGIN DISPLAY 36 144 PIN wr_en ATTR PinName + FONT 24 "Arial" +END DISPLAY +LINE N 0 176 32 176 +BEGIN DISPLAY 36 176 PIN wr_clk ATTR PinName + FONT 24 "Arial" +END DISPLAY +LINE N 0 240 32 240 +BEGIN DISPLAY 36 240 PIN rd_en ATTR PinName + FONT 24 "Arial" +END DISPLAY +LINE N 0 272 32 272 +BEGIN DISPLAY 36 272 PIN rd_clk ATTR PinName + FONT 24 "Arial" +END DISPLAY +LINE N 144 704 144 672 +BEGIN DISPLAY 144 668 PIN rst ATTR PinName + ALIGNMENT BCENTER + FONT 24 "Arial" +END DISPLAY +BEGIN LINE W 576 80 544 80 +END LINE +BEGIN DISPLAY 540 80 PIN dout[35:0] ATTR PinName + ALIGNMENT RIGHT + FONT 24 "Arial" +END DISPLAY +LINE N 576 208 544 208 +BEGIN DISPLAY 540 208 PIN full ATTR PinName + ALIGNMENT RIGHT + FONT 24 "Arial" +END DISPLAY +BEGIN LINE W 576 368 544 368 +END LINE +BEGIN DISPLAY 540 368 PIN wr_data_count[8:0] ATTR PinName + ALIGNMENT RIGHT + FONT 24 "Arial" +END DISPLAY +LINE N 576 432 544 432 +BEGIN DISPLAY 540 432 PIN empty ATTR PinName + ALIGNMENT RIGHT + FONT 24 "Arial" +END DISPLAY +BEGIN LINE W 576 592 544 592 +END LINE +BEGIN DISPLAY 540 592 PIN rd_data_count[8:0] ATTR PinName + ALIGNMENT RIGHT + FONT 24 "Arial" +END DISPLAY +END SYMBOL diff --git a/coregen/fifo_xlnx_512x36_2clk.v b/coregen/fifo_xlnx_512x36_2clk.v new file mode 100644 index 000000000..3cc5e29f0 --- /dev/null +++ b/coregen/fifo_xlnx_512x36_2clk.v @@ -0,0 +1,173 @@ +/******************************************************************************* +* This file is owned and controlled by Xilinx and must be used * +* solely for design, simulation, implementation and creation of * +* design files limited to Xilinx devices or technologies. Use * +* with non-Xilinx devices or technologies is expressly prohibited * +* and immediately terminates your license. * +* * +* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" * +* SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR * +* XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION * +* AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION * +* OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS * +* IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, * +* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE * +* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY * +* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE * +* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR * +* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF * +* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS * +* FOR A PARTICULAR PURPOSE. * +* * +* Xilinx products are not intended for use in life support * +* appliances, devices, or systems. Use in such applications are * +* expressly prohibited. * +* * +* (c) Copyright 1995-2007 Xilinx, Inc. * +* All rights reserved. * +*******************************************************************************/ +// The synthesis directives "translate_off/translate_on" specified below are +// supported by Xilinx, Mentor Graphics and Synplicity synthesis +// tools. Ensure they are correct for your synthesis tool(s). + +// You must compile the wrapper file fifo_xlnx_512x36_2clk.v when simulating +// the core, fifo_xlnx_512x36_2clk. When compiling the wrapper file, be sure to +// reference the XilinxCoreLib Verilog simulation library. For detailed +// instructions, please refer to the "CORE Generator Help". + +`timescale 1ns/1ps + +module fifo_xlnx_512x36_2clk( + din, + rd_clk, + rd_en, + rst, + wr_clk, + wr_en, + dout, + empty, + full, + rd_data_count, + wr_data_count); + + +input [35 : 0] din; +input rd_clk; +input rd_en; +input rst; +input wr_clk; +input wr_en; +output [35 : 0] dout; +output empty; +output full; +output [8 : 0] rd_data_count; +output [8 : 0] wr_data_count; + +// synthesis translate_off + + FIFO_GENERATOR_V4_3 #( + .C_COMMON_CLOCK(0), + .C_COUNT_TYPE(0), + .C_DATA_COUNT_WIDTH(9), + .C_DEFAULT_VALUE("BlankString"), + .C_DIN_WIDTH(36), + .C_DOUT_RST_VAL("0"), + .C_DOUT_WIDTH(36), + .C_ENABLE_RLOCS(0), + .C_FAMILY("spartan3"), + .C_FULL_FLAGS_RST_VAL(1), + .C_HAS_ALMOST_EMPTY(0), + .C_HAS_ALMOST_FULL(0), + .C_HAS_BACKUP(0), + .C_HAS_DATA_COUNT(0), + .C_HAS_INT_CLK(0), + .C_HAS_MEMINIT_FILE(0), + .C_HAS_OVERFLOW(0), + .C_HAS_RD_DATA_COUNT(1), + .C_HAS_RD_RST(0), + .C_HAS_RST(1), + .C_HAS_SRST(0), + .C_HAS_UNDERFLOW(0), + .C_HAS_VALID(0), + .C_HAS_WR_ACK(0), + .C_HAS_WR_DATA_COUNT(1), + .C_HAS_WR_RST(0), + .C_IMPLEMENTATION_TYPE(2), + .C_INIT_WR_PNTR_VAL(0), + .C_MEMORY_TYPE(1), + .C_MIF_FILE_NAME("BlankString"), + .C_MSGON_VAL(1), + .C_OPTIMIZATION_MODE(0), + .C_OVERFLOW_LOW(0), + .C_PRELOAD_LATENCY(0), + .C_PRELOAD_REGS(1), + .C_PRIM_FIFO_TYPE("512x36"), + .C_PROG_EMPTY_THRESH_ASSERT_VAL(4), + .C_PROG_EMPTY_THRESH_NEGATE_VAL(5), + .C_PROG_EMPTY_TYPE(0), + .C_PROG_FULL_THRESH_ASSERT_VAL(511), + .C_PROG_FULL_THRESH_NEGATE_VAL(510), + .C_PROG_FULL_TYPE(0), + .C_RD_DATA_COUNT_WIDTH(9), + .C_RD_DEPTH(512), + .C_RD_FREQ(1), + .C_RD_PNTR_WIDTH(9), + .C_UNDERFLOW_LOW(0), + .C_USE_DOUT_RST(0), + .C_USE_ECC(0), + .C_USE_EMBEDDED_REG(0), + .C_USE_FIFO16_FLAGS(0), + .C_USE_FWFT_DATA_COUNT(0), + .C_VALID_LOW(0), + .C_WR_ACK_LOW(0), + .C_WR_DATA_COUNT_WIDTH(9), + .C_WR_DEPTH(512), + .C_WR_FREQ(1), + .C_WR_PNTR_WIDTH(9), + .C_WR_RESPONSE_LATENCY(1)) + inst ( + .DIN(din), + .RD_CLK(rd_clk), + .RD_EN(rd_en), + .RST(rst), + .WR_CLK(wr_clk), + .WR_EN(wr_en), + .DOUT(dout), + .EMPTY(empty), + .FULL(full), + .RD_DATA_COUNT(rd_data_count), + .WR_DATA_COUNT(wr_data_count), + .CLK(), + .INT_CLK(), + .BACKUP(), + .BACKUP_MARKER(), + .PROG_EMPTY_THRESH(), + .PROG_EMPTY_THRESH_ASSERT(), + .PROG_EMPTY_THRESH_NEGATE(), + .PROG_FULL_THRESH(), + .PROG_FULL_THRESH_ASSERT(), + .PROG_FULL_THRESH_NEGATE(), + .RD_RST(), + .SRST(), + .WR_RST(), + .ALMOST_EMPTY(), + .ALMOST_FULL(), + .DATA_COUNT(), + .OVERFLOW(), + .PROG_EMPTY(), + .PROG_FULL(), + .VALID(), + .UNDERFLOW(), + .WR_ACK(), + .SBITERR(), + .DBITERR()); + + +// synthesis translate_on + +// XST black box declaration +// box_type "black_box" +// synthesis attribute box_type of fifo_xlnx_512x36_2clk is "black_box" + +endmodule + diff --git a/coregen/fifo_xlnx_512x36_2clk.veo b/coregen/fifo_xlnx_512x36_2clk.veo new file mode 100644 index 000000000..40747fd2f --- /dev/null +++ b/coregen/fifo_xlnx_512x36_2clk.veo @@ -0,0 +1,53 @@ +/******************************************************************************* +* This file is owned and controlled by Xilinx and must be used * +* solely for design, simulation, implementation and creation of * +* design files limited to Xilinx devices or technologies. Use * +* with non-Xilinx devices or technologies is expressly prohibited * +* and immediately terminates your license. * +* * +* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" * +* SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR * +* XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION * +* AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION * +* OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS * +* IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, * +* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE * +* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY * +* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE * +* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR * +* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF * +* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS * +* FOR A PARTICULAR PURPOSE. * +* * +* Xilinx products are not intended for use in life support * +* appliances, devices, or systems. Use in such applications are * +* expressly prohibited. * +* * +* (c) Copyright 1995-2007 Xilinx, Inc. * +* All rights reserved. * +*******************************************************************************/ +// The following must be inserted into your Verilog file for this +// core to be instantiated. Change the instance name and port connections +// (in parentheses) to your own signal names. + +//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG +fifo_xlnx_512x36_2clk YourInstanceName ( + .din(din), // Bus [35 : 0] + .rd_clk(rd_clk), + .rd_en(rd_en), + .rst(rst), + .wr_clk(wr_clk), + .wr_en(wr_en), + .dout(dout), // Bus [35 : 0] + .empty(empty), + .full(full), + .rd_data_count(rd_data_count), // Bus [8 : 0] + .wr_data_count(wr_data_count)); // Bus [8 : 0] + +// INST_TAG_END ------ End INSTANTIATION Template --------- + +// You must compile the wrapper file fifo_xlnx_512x36_2clk.v when simulating +// the core, fifo_xlnx_512x36_2clk. When compiling the wrapper file, be sure to +// reference the XilinxCoreLib Verilog simulation library. For detailed +// instructions, please refer to the "CORE Generator Help". + diff --git a/coregen/fifo_xlnx_512x36_2clk.vhd b/coregen/fifo_xlnx_512x36_2clk.vhd new file mode 100644 index 000000000..d9c2dd307 --- /dev/null +++ b/coregen/fifo_xlnx_512x36_2clk.vhd @@ -0,0 +1,156 @@ +-------------------------------------------------------------------------------- +-- This file is owned and controlled by Xilinx and must be used -- +-- solely for design, simulation, implementation and creation of -- +-- design files limited to Xilinx devices or technologies. Use -- +-- with non-Xilinx devices or technologies is expressly prohibited -- +-- and immediately terminates your license. -- +-- -- +-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" -- +-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR -- +-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION -- +-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION -- +-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS -- +-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, -- +-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE -- +-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY -- +-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE -- +-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR -- +-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF -- +-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -- +-- FOR A PARTICULAR PURPOSE. -- +-- -- +-- Xilinx products are not intended for use in life support -- +-- appliances, devices, or systems. Use in such applications are -- +-- expressly prohibited. -- +-- -- +-- (c) Copyright 1995-2007 Xilinx, Inc. -- +-- All rights reserved. -- +-------------------------------------------------------------------------------- +-- You must compile the wrapper file fifo_xlnx_512x36_2clk.vhd when simulating +-- the core, fifo_xlnx_512x36_2clk. When compiling the wrapper file, be sure to +-- reference the XilinxCoreLib VHDL simulation library. For detailed +-- instructions, please refer to the "CORE Generator Help". + +-- The synthesis directives "translate_off/translate_on" specified +-- below are supported by Xilinx, Mentor Graphics and Synplicity +-- synthesis tools. Ensure they are correct for your synthesis tool(s). + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +-- synthesis translate_off +Library XilinxCoreLib; +-- synthesis translate_on +ENTITY fifo_xlnx_512x36_2clk IS + port ( + din: IN std_logic_VECTOR(35 downto 0); + rd_clk: IN std_logic; + rd_en: IN std_logic; + rst: IN std_logic; + wr_clk: IN std_logic; + wr_en: IN std_logic; + dout: OUT std_logic_VECTOR(35 downto 0); + empty: OUT std_logic; + full: OUT std_logic; + rd_data_count: OUT std_logic_VECTOR(8 downto 0); + wr_data_count: OUT std_logic_VECTOR(8 downto 0)); +END fifo_xlnx_512x36_2clk; + +ARCHITECTURE fifo_xlnx_512x36_2clk_a OF fifo_xlnx_512x36_2clk IS +-- synthesis translate_off +component wrapped_fifo_xlnx_512x36_2clk + port ( + din: IN std_logic_VECTOR(35 downto 0); + rd_clk: IN std_logic; + rd_en: IN std_logic; + rst: IN std_logic; + wr_clk: IN std_logic; + wr_en: IN std_logic; + dout: OUT std_logic_VECTOR(35 downto 0); + empty: OUT std_logic; + full: OUT std_logic; + rd_data_count: OUT std_logic_VECTOR(8 downto 0); + wr_data_count: OUT std_logic_VECTOR(8 downto 0)); +end component; + +-- Configuration specification + for all : wrapped_fifo_xlnx_512x36_2clk use entity XilinxCoreLib.fifo_generator_v4_3(behavioral) + generic map( + c_has_int_clk => 0, + c_rd_freq => 1, + c_wr_response_latency => 1, + c_has_srst => 0, + c_has_rd_data_count => 1, + c_din_width => 36, + c_has_wr_data_count => 1, + c_full_flags_rst_val => 1, + c_implementation_type => 2, + c_family => "spartan3", + c_use_embedded_reg => 0, + c_has_wr_rst => 0, + c_wr_freq => 1, + c_use_dout_rst => 0, + c_underflow_low => 0, + c_has_meminit_file => 0, + c_has_overflow => 0, + c_preload_latency => 0, + c_dout_width => 36, + c_msgon_val => 1, + c_rd_depth => 512, + c_default_value => "BlankString", + c_mif_file_name => "BlankString", + c_has_underflow => 0, + c_has_rd_rst => 0, + c_has_almost_full => 0, + c_has_rst => 1, + c_data_count_width => 9, + c_has_wr_ack => 0, + c_use_ecc => 0, + c_wr_ack_low => 0, + c_common_clock => 0, + c_rd_pntr_width => 9, + c_use_fwft_data_count => 0, + c_has_almost_empty => 0, + c_rd_data_count_width => 9, + c_enable_rlocs => 0, + c_wr_pntr_width => 9, + c_overflow_low => 0, + c_prog_empty_type => 0, + c_optimization_mode => 0, + c_wr_data_count_width => 9, + c_preload_regs => 1, + c_dout_rst_val => "0", + c_has_data_count => 0, + c_prog_full_thresh_negate_val => 510, + c_wr_depth => 512, + c_prog_empty_thresh_negate_val => 5, + c_prog_empty_thresh_assert_val => 4, + c_has_valid => 0, + c_init_wr_pntr_val => 0, + c_prog_full_thresh_assert_val => 511, + c_use_fifo16_flags => 0, + c_has_backup => 0, + c_valid_low => 0, + c_prim_fifo_type => "512x36", + c_count_type => 0, + c_prog_full_type => 0, + c_memory_type => 1); +-- synthesis translate_on +BEGIN +-- synthesis translate_off +U0 : wrapped_fifo_xlnx_512x36_2clk + port map ( + din => din, + rd_clk => rd_clk, + rd_en => rd_en, + rst => rst, + wr_clk => wr_clk, + wr_en => wr_en, + dout => dout, + empty => empty, + full => full, + rd_data_count => rd_data_count, + wr_data_count => wr_data_count); +-- synthesis translate_on + +END fifo_xlnx_512x36_2clk_a; + diff --git a/coregen/fifo_xlnx_512x36_2clk.vho b/coregen/fifo_xlnx_512x36_2clk.vho new file mode 100644 index 000000000..70eac27a5 --- /dev/null +++ b/coregen/fifo_xlnx_512x36_2clk.vho @@ -0,0 +1,76 @@ +-------------------------------------------------------------------------------- +-- This file is owned and controlled by Xilinx and must be used -- +-- solely for design, simulation, implementation and creation of -- +-- design files limited to Xilinx devices or technologies. Use -- +-- with non-Xilinx devices or technologies is expressly prohibited -- +-- and immediately terminates your license. -- +-- -- +-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" -- +-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR -- +-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION -- +-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION -- +-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS -- +-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, -- +-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE -- +-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY -- +-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE -- +-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR -- +-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF -- +-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -- +-- FOR A PARTICULAR PURPOSE. -- +-- -- +-- Xilinx products are not intended for use in life support -- +-- appliances, devices, or systems. Use in such applications are -- +-- expressly prohibited. -- +-- -- +-- (c) Copyright 1995-2007 Xilinx, Inc. -- +-- All rights reserved. -- +-------------------------------------------------------------------------------- +-- The following code must appear in the VHDL architecture header: + +------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG +component fifo_xlnx_512x36_2clk + port ( + din: IN std_logic_VECTOR(35 downto 0); + rd_clk: IN std_logic; + rd_en: IN std_logic; + rst: IN std_logic; + wr_clk: IN std_logic; + wr_en: IN std_logic; + dout: OUT std_logic_VECTOR(35 downto 0); + empty: OUT std_logic; + full: OUT std_logic; + rd_data_count: OUT std_logic_VECTOR(8 downto 0); + wr_data_count: OUT std_logic_VECTOR(8 downto 0)); +end component; + +-- Synplicity black box declaration +attribute syn_black_box : boolean; +attribute syn_black_box of fifo_xlnx_512x36_2clk: component is true; + +-- COMP_TAG_END ------ End COMPONENT Declaration ------------ + +-- The following code must appear in the VHDL architecture +-- body. Substitute your own instance name and net names. + +------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG +your_instance_name : fifo_xlnx_512x36_2clk + port map ( + din => din, + rd_clk => rd_clk, + rd_en => rd_en, + rst => rst, + wr_clk => wr_clk, + wr_en => wr_en, + dout => dout, + empty => empty, + full => full, + rd_data_count => rd_data_count, + wr_data_count => wr_data_count); +-- INST_TAG_END ------ End INSTANTIATION Template ------------ + +-- You must compile the wrapper file fifo_xlnx_512x36_2clk.vhd when simulating +-- the core, fifo_xlnx_512x36_2clk. When compiling the wrapper file, be sure to +-- reference the XilinxCoreLib VHDL simulation library. For detailed +-- instructions, please refer to the "CORE Generator Help". + diff --git a/coregen/fifo_xlnx_512x36_2clk.xco b/coregen/fifo_xlnx_512x36_2clk.xco new file mode 100644 index 000000000..c67e7e89f --- /dev/null +++ b/coregen/fifo_xlnx_512x36_2clk.xco @@ -0,0 +1,82 @@ +############################################################## +# +# Xilinx Core Generator version K.31 +# Date: Mon Jul 28 22:47:43 2008 +# +############################################################## +# +# This file contains the customisation parameters for a +# Xilinx CORE Generator IP GUI. It is strongly recommended +# that you do not manually alter this file as it may cause +# unexpected and unsupported behavior. +# +############################################################## +# +# BEGIN Project Options +SET addpads = False +SET asysymbol = True +SET busformat = BusFormatAngleBracketNotRipped +SET createndf = False +SET designentry = VHDL +SET device = xc3s2000 +SET devicefamily = spartan3 +SET flowvendor = Foundation_iSE +SET formalverification = False +SET foundationsym = False +SET implementationfiletype = Ngc +SET package = fg456 +SET removerpms = False +SET simulationfiles = Behavioral +SET speedgrade = -5 +SET verilogsim = True +SET vhdlsim = True +# END Project Options +# BEGIN Select +SELECT Fifo_Generator family Xilinx,_Inc. 4.3 +# END Select +# BEGIN Parameters +CSET almost_empty_flag=false +CSET almost_full_flag=false +CSET component_name=fifo_xlnx_512x36_2clk +CSET data_count=false +CSET data_count_width=9 +CSET disable_timing_violations=false +CSET dout_reset_value=0 +CSET empty_threshold_assert_value=4 +CSET empty_threshold_negate_value=5 +CSET enable_ecc=false +CSET enable_int_clk=false +CSET fifo_implementation=Independent_Clocks_Block_RAM +CSET full_flags_reset_value=1 +CSET full_threshold_assert_value=511 +CSET full_threshold_negate_value=510 +CSET input_data_width=36 +CSET input_depth=512 +CSET output_data_width=36 +CSET output_depth=512 +CSET overflow_flag=false +CSET overflow_sense=Active_High +CSET performance_options=First_Word_Fall_Through +CSET programmable_empty_type=No_Programmable_Empty_Threshold +CSET programmable_full_type=No_Programmable_Full_Threshold +CSET read_clock_frequency=1 +CSET read_data_count=true +CSET read_data_count_width=9 +CSET reset_pin=true +CSET reset_type=Asynchronous_Reset +CSET underflow_flag=false +CSET underflow_sense=Active_High +CSET use_dout_reset=false +CSET use_embedded_registers=false +CSET use_extra_logic=false +CSET valid_flag=false +CSET valid_sense=Active_High +CSET write_acknowledge_flag=false +CSET write_acknowledge_sense=Active_High +CSET write_clock_frequency=1 +CSET write_data_count=true +CSET write_data_count_width=9 +# END Parameters +GENERATE +# CRC: 43b7cba0 + diff --git a/coregen/fifo_xlnx_512x36_2clk_fifo_generator_v4_3_xst_1.lso b/coregen/fifo_xlnx_512x36_2clk_fifo_generator_v4_3_xst_1.lso new file mode 100644 index 000000000..f1a6f7899 --- /dev/null +++ b/coregen/fifo_xlnx_512x36_2clk_fifo_generator_v4_3_xst_1.lso @@ -0,0 +1,3 @@ +blkmemdp_v6_2 +blk_mem_gen_v2_6 +fifo_generator_v4_3 diff --git a/coregen/fifo_xlnx_512x36_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt b/coregen/fifo_xlnx_512x36_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt new file mode 100644 index 000000000..5abd4e097 --- /dev/null +++ b/coregen/fifo_xlnx_512x36_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt @@ -0,0 +1,103 @@ +<?xml version="1.0" encoding="UTF-8" standalone="yes" ?> +<document OS="lin" product="ISE" version="10.1"> + + <!--The data in this file is primarily intended for consumption by Xilinx tools. + The structure and the elements are likely to change over the next few releases. + This means code written to parse this file will need to be revisited each subsequent release.--> + + <application stringID="Xst" timeStamp="Mon Jul 28 15:46:26 2008"> + <section stringID="XST_HDL_SYNTHESIS_REPORT"> + <item dataType="int" stringID="XST_ADDERSSUBTRACTORS" value="2"></item> + <item dataType="int" stringID="XST_COUNTERS" value="2"> + <item dataType="int" stringID="XST_9BIT_UP_COUNTER" value="2"/> + </item> + <item dataType="int" stringID="XST_REGISTERS" value="31"> + <item dataType="int" stringID="XST_1BIT_REGISTER" value="15"/> + <item dataType="int" stringID="XST_2BIT_REGISTER" value="1"/> + <item dataType="int" stringID="XST_3BIT_REGISTER" value="1"/> + <item dataType="int" stringID="XST_36BIT_REGISTER" value="1"/> + <item dataType="int" stringID="XST_9BIT_REGISTER" value="13"/> + </item> + <item dataType="int" stringID="XST_XORS" value="68"> + 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stringID="XST_NO_PARTITIONS_WERE_FOUND_IN_THIS_DESIGN"/> + </section> + </section> + <section stringID="XST_FINAL_REPORT"> + <section stringID="XST_FINAL_RESULTS"> + <item stringID="XST_TOP_LEVEL_OUTPUT_FILE_NAME" value="/home/matt/coregen/tmp/_cg/fifo_xlnx_512x36_2clk_fifo_generator_v4_3_xst_1.ngc"/> + <item stringID="XST_OUTPUT_FORMAT" value="NGC"/> + <item stringID="XST_OPTIMIZATION_GOAL" value="SPEED"/> + <item stringID="XST_KEEP_HIERARCHY" value="no"/> + </section> + <section stringID="XST_DESIGN_STATISTICS"> + <item stringID="XST_IOS" value="177"/> + </section> + <section stringID="XST_CELL_USAGE"> + <item dataType="int" stringID="XST_BELS" value="193"> + <item dataType="int" stringID="XST_GND" value="1"/> + <item dataType="int" stringID="XST_LUT1" value="18"/> + <item dataType="int" stringID="XST_LUT2" value="45"/> + <item dataType="int" stringID="XST_LUT2L" value="2"/> + <item dataType="int" stringID="XST_LUT3" value="7"/> + <item dataType="int" stringID="XST_LUT3L" value="2"/> + <item dataType="int" stringID="XST_LUT4" value="29"/> + <item dataType="int" stringID="XST_MUXCY" value="52"/> + <item dataType="int" stringID="XST_VCC" value="1"/> + <item dataType="int" stringID="XST_XORCY" value="36"/> + </item> + <item dataType="int" stringID="XST_FLIPFLOPSLATCHES" value="188"> + <item dataType="int" stringID="XST_FD" value="4"/> + <item dataType="int" stringID="XST_FDC" value="92"/> + <item dataType="int" stringID="XST_FDCE" value="42"/> + <item dataType="int" stringID="XST_FDE" value="36"/> + <item dataType="int" stringID="XST_FDP" value="9"/> + <item dataType="int" stringID="XST_FDPE" value="5"/> + </item> + <item dataType="int" stringID="XST_RAMS" value="1"> + <item dataType="int" stringID="XST_RAMB16S36S36" value="1"/> + </item> + </section> + </section> + <section stringID="XST_DEVICE_UTILIZATION_SUMMARY"> + <item stringID="XST_SELECTED_DEVICE" value="3s2000fg456-5"/> + <item AVAILABLE="20480" dataType="int" stringID="XST_NUMBER_OF_SLICES" value="123"/> + <item AVAILABLE="40960" dataType="int" stringID="XST_NUMBER_OF_SLICE_FLIP_FLOPS" value="188"/> + <item AVAILABLE="40960" dataType="int" stringID="XST_NUMBER_OF_4_INPUT_LUTS" value="103"/> + <item dataType="int" stringID="XST_NUMBER_OF_IOS" value="177"/> + <item AVAILABLE="333" dataType="int" stringID="XST_NUMBER_OF_BONDED_IOBS" value="0"/> + <item AVAILABLE="40" dataType="int" stringID="XST_NUMBER_OF_BRAMS" value="1"/> + </section> + <section stringID="XST_PARTITION_RESOURCE_SUMMARY"> + <section stringID="XST_NO_PARTITIONS_WERE_FOUND_IN_THIS_DESIGN"/> + </section> + <section stringID="XST_ERRORS_STATISTICS"> + <item dataType="int" filtered="0" stringID="XST_NUMBER_OF_ERRORS" value="0"/> + <item dataType="int" filtered="0" stringID="XST_NUMBER_OF_WARNINGS" value="131"/> + <item dataType="int" filtered="0" stringID="XST_NUMBER_OF_INFOS" value="16"/> + </section> + </application> + +</document> diff --git a/coregen/fifo_xlnx_512x36_2clk_flist.txt b/coregen/fifo_xlnx_512x36_2clk_flist.txt new file mode 100644 index 000000000..e9d38a49b --- /dev/null +++ b/coregen/fifo_xlnx_512x36_2clk_flist.txt @@ -0,0 +1,12 @@ +# Output products list for <fifo_xlnx_512x36_2clk> +fifo_xlnx_512x36_2clk.asy +fifo_xlnx_512x36_2clk.ngc +fifo_xlnx_512x36_2clk.sym +fifo_xlnx_512x36_2clk.v +fifo_xlnx_512x36_2clk.veo +fifo_xlnx_512x36_2clk.vhd +fifo_xlnx_512x36_2clk.vho +fifo_xlnx_512x36_2clk.xco +fifo_xlnx_512x36_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt +fifo_xlnx_512x36_2clk_flist.txt +fifo_xlnx_512x36_2clk_xmdf.tcl diff --git a/coregen/fifo_xlnx_512x36_2clk_readme.txt b/coregen/fifo_xlnx_512x36_2clk_readme.txt new file mode 100644 index 000000000..07bf20790 --- /dev/null +++ b/coregen/fifo_xlnx_512x36_2clk_readme.txt @@ -0,0 +1,55 @@ +The following files were generated for 'fifo_xlnx_512x36_2clk' in directory +/home/jblum/proj/usrp2/trunk/fpga/coregen/: + +fifo_xlnx_512x36_2clk.asy: + Graphical symbol information file. Used by the ISE tools and some + third party tools to create a symbol representing the core. + +fifo_xlnx_512x36_2clk.ngc: + Binary Xilinx implementation netlist file containing the information + required to implement the module in a Xilinx (R) FPGA. + +fifo_xlnx_512x36_2clk.sym: + Please see the core data sheet. + +fifo_xlnx_512x36_2clk.v: + Verilog wrapper file provided to support functional simulation. + This file contains simulation model customization data that is + passed to a parameterized simulation model for the core. + +fifo_xlnx_512x36_2clk.veo: + VEO template file containing code that can be used as a model for + instantiating a CORE Generator module in a Verilog design. + +fifo_xlnx_512x36_2clk.vhd: + VHDL wrapper file provided to support functional simulation. This + file contains simulation model customization data that is passed to + a parameterized simulation model for the core. + +fifo_xlnx_512x36_2clk.vho: + VHO template file containing code that can be used as a model for + instantiating a CORE Generator module in a VHDL design. + +fifo_xlnx_512x36_2clk.xco: + CORE Generator input file containing the parameters used to + regenerate a core. + +fifo_xlnx_512x36_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt: + Please see the core data sheet. + +fifo_xlnx_512x36_2clk_flist.txt: + Text file listing all of the output files produced when a customized + core was generated in the CORE Generator. + +fifo_xlnx_512x36_2clk_readme.txt: + Text file indicating the files generated and how they are used. + +fifo_xlnx_512x36_2clk_xmdf.tcl: + ISE Project Navigator interface file. ISE uses this file to determine + how the files output by CORE Generator for the core can be integrated + into your ISE project. + + +Please see the Xilinx CORE Generator online help for further details on +generated files and how to use them. + diff --git a/coregen/fifo_xlnx_512x36_2clk_xmdf.tcl b/coregen/fifo_xlnx_512x36_2clk_xmdf.tcl new file mode 100644 index 000000000..42a681df9 --- /dev/null +++ b/coregen/fifo_xlnx_512x36_2clk_xmdf.tcl @@ -0,0 +1,84 @@ +# The package naming convention is <core_name>_xmdf +package provide fifo_xlnx_512x36_2clk_xmdf 1.0 + +# This includes some utilities that support common XMDF operations +package require utilities_xmdf + +# Define a namespace for this package. The name of the name space +# is <core_name>_xmdf +namespace eval ::fifo_xlnx_512x36_2clk_xmdf { +# Use this to define any statics +} + +# Function called by client to rebuild the params and port arrays +# Optional when the use context does not require the param or ports +# arrays to be available. +proc ::fifo_xlnx_512x36_2clk_xmdf::xmdfInit { instance } { +# Variable containg name of library into which module is compiled +# Recommendation: <module_name> +# Required +utilities_xmdf::xmdfSetData $instance Module Attributes Name fifo_xlnx_512x36_2clk +} +# ::fifo_xlnx_512x36_2clk_xmdf::xmdfInit + +# Function called by client to fill in all the xmdf* data variables +# based on the current settings of the parameters +proc ::fifo_xlnx_512x36_2clk_xmdf::xmdfApplyParams { instance } { + +set fcount 0 +# Array containing libraries that are assumed to exist +# Examples include unisim and xilinxcorelib +# Optional +# In this example, we assume that the unisim library will +# be magically +# available to the simulation and synthesis tool +utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library +utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_512x36_2clk.asy +utilities_xmdf::xmdfSetData $instance FileSet $fcount type asy +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_512x36_2clk.ngc +utilities_xmdf::xmdfSetData $instance FileSet $fcount type ngc +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_512x36_2clk.sym +utilities_xmdf::xmdfSetData $instance FileSet $fcount type symbol +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_512x36_2clk.v +utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_512x36_2clk.veo +utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog_template +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_512x36_2clk.vhd +utilities_xmdf::xmdfSetData $instance FileSet $fcount type vhdl +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_512x36_2clk.vho +utilities_xmdf::xmdfSetData $instance FileSet $fcount type vhdl_template +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_512x36_2clk.xco +utilities_xmdf::xmdfSetData $instance FileSet $fcount type coregen_ip +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_512x36_2clk_fifo_generator_v4_3_xst_1.ngc_xst.xrpt +utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_xlnx_512x36_2clk_xmdf.tcl +utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView +incr fcount + +utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module fifo_xlnx_512x36_2clk +incr fcount + +} + +# ::gen_comp_name_xmdf::xmdfApplyParams |