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authorMatt Ettus <matt@ettus.com>2010-01-15 15:32:23 -0800
committerMatt Ettus <matt@ettus.com>2010-01-15 15:32:23 -0800
commitffad1ae6b2a81e205ef53a871a848face9089ad4 (patch)
tree1ec135b30556ca9545f56b97c2657ecc584d2e8f /control_lib
parente60bffc646a8fa7b3466da70f3d71a15abb0d3f1 (diff)
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yet more debug lines
Diffstat (limited to 'control_lib')
-rw-r--r--control_lib/newfifo/fifo19_to_fifo36.v7
1 files changed, 5 insertions, 2 deletions
diff --git a/control_lib/newfifo/fifo19_to_fifo36.v b/control_lib/newfifo/fifo19_to_fifo36.v
index e22ca0a49..8a65d5189 100644
--- a/control_lib/newfifo/fifo19_to_fifo36.v
+++ b/control_lib/newfifo/fifo19_to_fifo36.v
@@ -7,7 +7,8 @@ module fifo19_to_fifo36
output [35:0] f36_dataout,
output f36_src_rdy_o,
- input f36_dst_rdy_i
+ input f36_dst_rdy_i,
+ output [31:0] debug
);
reg f36_sof, f36_eof, f36_occ;
@@ -67,5 +68,7 @@ module fifo19_to_fifo36
assign f19_dst_rdy_o = xfer_out | (state != 2);
assign f36_dataout = {f36_occ,f36_eof,f36_sof,dat0,dat1};
assign f36_src_rdy_o = (state == 2);
-
+
+ assign debug = state;
+
endmodule // fifo19_to_fifo36