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author | Matt Ettus <matt@ettus.com> | 2009-09-04 22:14:21 -0700 |
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committer | Matt Ettus <matt@ettus.com> | 2009-09-04 22:14:21 -0700 |
commit | e50bab11b3cdc30ffebb51f64ffe9f0ef74bdc55 (patch) | |
tree | 19aa7f1a16971dba775a852dbdabf7c8f8640e41 /control_lib | |
parent | 74d9370a8be4783183e27673727f91ef772b9726 (diff) | |
download | uhd-e50bab11b3cdc30ffebb51f64ffe9f0ef74bdc55.tar.gz uhd-e50bab11b3cdc30ffebb51f64ffe9f0ef74bdc55.tar.bz2 uhd-e50bab11b3cdc30ffebb51f64ffe9f0ef74bdc55.zip |
remove unused old style fifo
Diffstat (limited to 'control_lib')
-rw-r--r-- | control_lib/fifo_2clock_casc.v | 31 |
1 files changed, 0 insertions, 31 deletions
diff --git a/control_lib/fifo_2clock_casc.v b/control_lib/fifo_2clock_casc.v deleted file mode 100644 index e9b0cfc25..000000000 --- a/control_lib/fifo_2clock_casc.v +++ /dev/null @@ -1,31 +0,0 @@ - -module fifo_2clock_casc - #(parameter DWIDTH=32, AWIDTH=9) - (input wclk, input [DWIDTH-1:0] datain, input write, output full, output [AWIDTH-1:0] level_wclk, - input rclk, output [DWIDTH-1:0] dataout, input read, output empty, output [AWIDTH-1:0] level_rclk, - input arst); - - wire full_int, empty_int, full_int2, empty_int2, transfer, transfer2; - wire [DWIDTH-1:0] data_int, data_int2; - - shortfifo #(.WIDTH(DWIDTH)) shortfifo - (.clk(wclk), .rst(arst), .clear(0), - .datain(datain), .write(write), .full(full), - .dataout(data_int), .read(transfer), .empty(empty_int) ); - - assign transfer = ~full_int & ~empty_int; - - fifo_2clock #(.DWIDTH(DWIDTH),.AWIDTH(AWIDTH)) fifo_2clock - (.wclk(wclk), .datain(data_int), .write(transfer), .full(full_int), .level_wclk(level_wclk), - .rclk(rclk), .dataout(data_int2), .read(transfer2), .empty(empty_int2), .level_rclk(level_rclk), - .arst(arst) ); - - assign transfer2 = ~full_int2 & ~empty_int2; - - shortfifo #(.WIDTH(DWIDTH)) shortfifo2 - (.clk(rclk), .rst(arst), .clear(0), - .datain(data_int2), .write(transfer2), .full(full_int2), - .dataout(dataout), .read(read), .empty(empty) ); - -endmodule // fifo_2clock_casc - |