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author | Matt Ettus <matt@ettus.com> | 2009-11-05 16:05:32 -0800 |
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committer | Matt Ettus <matt@ettus.com> | 2009-11-05 16:05:32 -0800 |
commit | a14a987ea5781d457aac1d7aca6937b27aaa53e0 (patch) | |
tree | 877330f86c62b1d7d02a5bc5a56e2987e90e1d14 /control_lib | |
parent | 75f85f71aa34e5cd08feb983a2ff98f5a24bc1d2 (diff) | |
download | uhd-a14a987ea5781d457aac1d7aca6937b27aaa53e0.tar.gz uhd-a14a987ea5781d457aac1d7aca6937b27aaa53e0.tar.bz2 uhd-a14a987ea5781d457aac1d7aca6937b27aaa53e0.zip |
vita rx instead of rx_control. Ready for firmware testing. Misses timing by a little bit, will worry later.
Diffstat (limited to 'control_lib')
-rw-r--r-- | control_lib/setting_reg.v | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/control_lib/setting_reg.v b/control_lib/setting_reg.v index ccbaa3d2e..c8aff230f 100644 --- a/control_lib/setting_reg.v +++ b/control_lib/setting_reg.v @@ -1,14 +1,14 @@ module setting_reg - #(parameter my_addr = 0) + #(parameter my_addr = 0, parameter at_reset=32'd0) (input clk, input rst, input strobe, input wire [7:0] addr, input wire [31:0] in, output reg [31:0] out, output reg changed); always @(posedge clk) if(rst) begin - out <= 32'd0; + out <= at_reset; changed <= 1'b0; end else |