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| author | Matt Ettus <matt@ettus.com> | 2009-10-05 02:15:10 -0700 |
|---|---|---|
| committer | Matt Ettus <matt@ettus.com> | 2009-10-05 02:15:10 -0700 |
| commit | 32ed167c8f41ad698672ed803e409bb92c6d0074 (patch) | |
| tree | bdb561f3501a4c466ecb73a45ceaaf73f42f84d5 /control_lib | |
| parent | 1ff74777e47f3a2edefc5154484f2bdcb86c1a13 (diff) | |
| download | uhd-32ed167c8f41ad698672ed803e409bb92c6d0074.tar.gz uhd-32ed167c8f41ad698672ed803e409bb92c6d0074.tar.bz2 uhd-32ed167c8f41ad698672ed803e409bb92c6d0074.zip | |
Properly reset the fifos. We didn't connect before.
Diffstat (limited to 'control_lib')
| -rw-r--r-- | control_lib/newfifo/fifo_2clock.v | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/control_lib/newfifo/fifo_2clock.v b/control_lib/newfifo/fifo_2clock.v index 07ae090f2..34c85ccb4 100644 --- a/control_lib/newfifo/fifo_2clock.v +++ b/control_lib/newfifo/fifo_2clock.v @@ -19,28 +19,28 @@ module fifo_2clock if(WIDTH==36) if(SIZE==9) fifo_xlnx_512x36_2clk fifo_xlnx_512x36_2clk - (.rst(rst), + (.rst(arst), .wr_clk(wclk),.din(datain),.full(full),.wr_en(write),.wr_data_count(level_wclk), .rd_clk(rclk),.dout(dataout),.empty(empty),.rd_en(read),.rd_data_count(level_rclk) ); else if(SIZE==11) fifo_xlnx_2Kx36_2clk fifo_xlnx_2Kx36_2clk - (.rst(rst), + (.rst(arst), .wr_clk(wclk),.din(datain),.full(full),.wr_en(write),.wr_data_count(level_wclk), .rd_clk(rclk),.dout(dataout),.empty(empty),.rd_en(read),.rd_data_count(level_rclk) ); else if(SIZE==6) fifo_xlnx_64x36_2clk fifo_xlnx_64x36_2clk - (.rst(rst), + (.rst(arst), .wr_clk(wclk),.din(datain),.full(full),.wr_en(write),.wr_data_count(level_wclk), .rd_clk(rclk),.dout(dataout),.empty(empty),.rd_en(read),.rd_data_count(level_rclk) ); else fifo_xlnx_512x36_2clk fifo_xlnx_512x36_2clk - (.rst(rst), + (.rst(arst), .wr_clk(wclk),.din(datain),.full(full),.wr_en(write),.wr_data_count(level_wclk), .rd_clk(rclk),.dout(dataout),.empty(empty),.rd_en(read),.rd_data_count(level_rclk) ); else if((WIDTH==19)|(WIDTH==18)) if(SIZE==4) fifo_xlnx_16x19_2clk fifo_xlnx_16x19_2clk - (.rst(rst), + (.rst(arst), .wr_clk(wclk),.din(datain),.full(full),.wr_en(write),.wr_data_count(level_wclk), .rd_clk(rclk),.dout(dataout),.empty(empty),.rd_en(read),.rd_data_count(level_rclk) ); endgenerate |