More xilinx fifos, more clean up of our fifos

3 files changed, 27 insertions, 129 deletions

diff --git a/control_lib/cascadefifo2.v b/control_lib/cascadefifo2.v
deleted file mode 100644
index 984cc46e6..000000000
--- a/control_lib/cascadefifo2.v
+++ /dev/null
@@ -1,56 +0,0 @@
-
-
-// This FIFO exists to provide an intermediate point for the data on its
-// long trek from one RAM (in the buffer pool) to another (in the longfifo)
-// The shortfifo is more flexible in its placement since it is based on
-// distributed RAM
-
-// This one has the shortfifo on both the in and out sides.
-module cascadefifo2
-  #(parameter WIDTH=32, SIZE=9)
-    (input clk, input rst,
-     input [WIDTH-1:0] datain,
-     output [WIDTH-1:0] dataout,
-     input read,
-     input write,
-     input clear,
-     output full,
-     output empty,
-     output [15:0] space,
-     output [15:0] occupied);
-
-   wire [WIDTH-1:0] data_int, data_int2;
-   wire 	    empty_int, full_int, transfer;
-   wire 	    empty_int2, full_int2, transfer2;
-   wire [4:0] 	    s1_space, s1_occupied, s2_space, s2_occupied;
-   wire [15:0] 	    l_space, l_occupied;
-   
-   shortfifo #(.WIDTH(WIDTH)) shortfifo
-     (.clk(clk),.rst(rst),.clear(clear),
-      .datain(datain), .write(write), .full(full),
-      .dataout(data_int), .read(transfer), .empty(empty_int),
-      .space(s1_space),.occupied(s1_occupied) );
-      
-   longfifo #(.WIDTH(WIDTH),.SIZE(SIZE)) longfifo
-     (.clk(clk),.rst(rst),.clear(clear),
-      .datain(data_int), .write(transfer), .full(full_int),
-      .dataout(data_int2), .read(transfer2), .empty(empty_int2),
-      .space(l_space),.occupied(l_occupied) );
-   
-   shortfifo #(.WIDTH(WIDTH)) shortfifo2
-     (.clk(clk),.rst(rst),.clear(clear),
-      .datain(data_int2), .write(transfer2), .full(full_int2),
-      .dataout(dataout), .read(read), .empty(empty),
-      .space(s2_space),.occupied(s2_occupied) );
-   
-   assign 	    transfer = ~empty_int & ~full_int; 	    
-   assign 	    transfer2 = ~empty_int2 & ~full_int2; 	    
-   
-   assign 	    space = {11'b0,s1_space} + {11'b0,s2_space} + l_space;
-   assign 	    occupied = {11'b0,s1_occupied} + {11'b0,s2_occupied} + l_occupied;
-      
-endmodule // cascadefifo2
-
-
-
-
diff --git a/control_lib/newfifo/fifo18_to_ll8.v b/control_lib/newfifo/fifo18_to_ll8.v
deleted file mode 100644
index 4653244ef..000000000
--- a/control_lib/newfifo/fifo18_to_ll8.v
+++ /dev/null
@@ -1,58 +0,0 @@
-
-module fifo18_to_ll8
-  (input clk, input reset, input clear,
-   input [35:0] f18_data,
-   input f18_src_rdy_i,
-   output f18_dst_rdy_o,
-
-   output reg [7:0] ll_data,
-   output ll_sof_n,
-   output ll_eof_n,
-   output ll_src_rdy_n,
-   input ll_dst_rdy_n);
-
-   wire  ll_sof, ll_eof, ll_src_rdy;
-   assign ll_sof_n = ~ll_sof;
-   assign ll_eof_n = ~ll_eof;
-   assign ll_src_rdy_n = ~ll_src_rdy;
-   wire ll_dst_rdy = ~ll_dst_rdy_n;
-
-   wire   f18_sof = f18_data[32];
-   wire   f18_eof = f18_data[33];
-   wire   f18_occ = f18_data[35:34];
-   wire advance, end_early;
-   reg [1:0] state;
-   assign debug    = {29'b0,state};
-
-   always @(posedge clk)
-     if(reset)
-       state 	  <= 0;
-     else
-       if(advance)
-	 if(ll_eof)
-	   state  <= 0;
-	 else
-	   state  <= state + 1;
-
-   always @*
-     case(state)
-       0 : ll_data = f18_data[31:24];
-       1 : ll_data = f18_data[23:16];
-       2 : ll_data = f18_data[15:8];
-       3 : ll_data = f18_data[7:0];
-       default : ll_data = f18_data[31:24];
-       endcase // case (state)
-   
-   assign ll_sof 	 = (state==0) & f18_sof;
-   assign ll_eof 	 = f18_eof & (((state==0)&(f18_occ==1)) |
-			       ((state==1)&(f18_occ==2)) |
-			       ((state==2)&(f18_occ==3)) |
-			       (state==3));
-   
-   assign ll_src_rdy 	 = f18_src_rdy_i;
-
-   assign advance 	 = ll_src_rdy & ll_dst_rdy;
-   assign f18_dst_rdy_o  = advance & ((state==3)|ll_eof);
-   assign debug 	 = state;
-   
-endmodule // ll8_to_fifo36
diff --git a/control_lib/newfifo/fifo_2clock.v b/control_lib/newfifo/fifo_2clock.v
index 2ada39fb0..07ae090f2 100644
--- a/control_lib/newfifo/fifo_2clock.v
+++ b/control_lib/newfifo/fifo_2clock.v
@@ -16,21 +16,33 @@ module fifo_2clock
    assign read 	     = src_rdy_o & dst_rdy_i;
 
    generate
-      if(SIZE==9)
-	fifo_xlnx_512x36_2clk mac_tx_fifo_2clk
-	      (.rst(rst),
-	       .wr_clk(wclk),.din(datain),.full(full),.wr_en(write),.wr_data_count(level_wclk),
-	       .rd_clk(rclk),.dout(dataout),.empty(empty),.rd_en(read),.rd_data_count(level_rclk) );
-      else if(SIZE==11)
-	fifo_xlnx_2Kx36_2clk mac_tx_fifo_2clk
-	      (.rst(rst),
-	       .wr_clk(wclk),.din(datain),.full(full),.wr_en(write),.wr_data_count(level_wclk),
-	       .rd_clk(rclk),.dout(dataout),.empty(empty),.rd_en(read),.rd_data_count(level_rclk) );
-      else if(SIZE==6)
-	fifo_xlnx_64x36_2clk mac_tx_fifo_2clk
-		   (.rst(rst),
-		    .wr_clk(wclk),.din(datain),.full(full),.wr_en(write),.wr_data_count(level_wclk),
-		    .rd_clk(rclk),.dout(dataout),.empty(empty),.rd_en(read),.rd_data_count(level_rclk) );
+      if(WIDTH==36)
+	if(SIZE==9)
+	  fifo_xlnx_512x36_2clk fifo_xlnx_512x36_2clk
+	       (.rst(rst),
+		.wr_clk(wclk),.din(datain),.full(full),.wr_en(write),.wr_data_count(level_wclk),
+		.rd_clk(rclk),.dout(dataout),.empty(empty),.rd_en(read),.rd_data_count(level_rclk) );
+	else if(SIZE==11)
+	  fifo_xlnx_2Kx36_2clk fifo_xlnx_2Kx36_2clk 
+		     (.rst(rst),
+		      .wr_clk(wclk),.din(datain),.full(full),.wr_en(write),.wr_data_count(level_wclk),
+		      .rd_clk(rclk),.dout(dataout),.empty(empty),.rd_en(read),.rd_data_count(level_rclk) );
+	else if(SIZE==6)
+	  fifo_xlnx_64x36_2clk fifo_xlnx_64x36_2clk 
+		     (.rst(rst),
+		      .wr_clk(wclk),.din(datain),.full(full),.wr_en(write),.wr_data_count(level_wclk),
+		      .rd_clk(rclk),.dout(dataout),.empty(empty),.rd_en(read),.rd_data_count(level_rclk) );
+	else
+	  fifo_xlnx_512x36_2clk fifo_xlnx_512x36_2clk
+	       (.rst(rst),
+		.wr_clk(wclk),.din(datain),.full(full),.wr_en(write),.wr_data_count(level_wclk),
+		.rd_clk(rclk),.dout(dataout),.empty(empty),.rd_en(read),.rd_data_count(level_rclk) );
+      else if((WIDTH==19)|(WIDTH==18))
+	if(SIZE==4)
+	  fifo_xlnx_16x19_2clk fifo_xlnx_16x19_2clk
+		     (.rst(rst),
+		      .wr_clk(wclk),.din(datain),.full(full),.wr_en(write),.wr_data_count(level_wclk),
+		      .rd_clk(rclk),.dout(dataout),.empty(empty),.rd_en(read),.rd_data_count(level_rclk) );
    endgenerate
    
    assign occupied  = {{(16-SIZE-1){1'b0}},level_rclk};