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authorjcorgan <jcorgan@221aa14e-8319-0410-a670-987f0aec2ac5>2008-09-08 01:00:12 +0000
committerjcorgan <jcorgan@221aa14e-8319-0410-a670-987f0aec2ac5>2008-09-08 01:00:12 +0000
commit61f2f0214c5999ea42a368a4fc99f03d8eb28d1e (patch)
treee7e24a9adc05ff1422fe3ada9926a51634741b47 /control_lib/wb_output_pins32.v
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Merged r9433:9527 from features/gr-usrp2 into trunk. Adds usrp2 and gr-usrp2 top-level components. Trunk passes distcheck with mb-gcc installed, but currently not without them. The key issue is that when mb-gcc is not installed, the build system skips over the usrp2/firmware directory, and the firmware include files don't get put into the dist tarball. But we can't do the usual DIST_SUBDIRS method as the firmware is a subpackage.
git-svn-id: http://gnuradio.org/svn/gnuradio/trunk@9528 221aa14e-8319-0410-a670-987f0aec2ac5
Diffstat (limited to 'control_lib/wb_output_pins32.v')
-rw-r--r--control_lib/wb_output_pins32.v49
1 files changed, 49 insertions, 0 deletions
diff --git a/control_lib/wb_output_pins32.v b/control_lib/wb_output_pins32.v
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+
+
+// Simple 32-bit Wishbone compatible slave output port
+// with 8-bit granularity, modeled after the one in the spec
+// Allows for readback
+// Assumes a 32-bit wishbone bus
+// Lowest order bits get sel[0]
+//
+
+module wb_output_pins32
+ (wb_rst_i, wb_clk_i, wb_dat_i, wb_dat_o,
+ wb_we_i, wb_sel_i, wb_stb_i, wb_ack_o, wb_cyc_i,
+ port_output);
+
+ input wb_rst_i;
+ input wb_clk_i;
+ input wire [31:0] wb_dat_i;
+ output wire [31:0] wb_dat_o;
+ input wb_we_i;
+ input wire [3:0] wb_sel_i;
+ input wb_stb_i;
+ output wb_ack_o;
+ input wb_cyc_i;
+
+ output wire [31:0] port_output;
+
+ reg [31:0] internal_reg;
+
+ always @(posedge wb_clk_i)
+ if(wb_rst_i)
+ internal_reg <= #1 32'b0;
+ else
+ begin
+ if(wb_stb_i & wb_we_i & wb_sel_i[0])
+ internal_reg[7:0] <= #1 wb_dat_i[7:0];
+ if(wb_stb_i & wb_we_i & wb_sel_i[1])
+ internal_reg[15:8] <= #1 wb_dat_i[15:8];
+ if(wb_stb_i & wb_we_i & wb_sel_i[2])
+ internal_reg[23:16] <= #1 wb_dat_i[23:16];
+ if(wb_stb_i & wb_we_i & wb_sel_i[3])
+ internal_reg[31:24] <= #1 wb_dat_i[31:24];
+ end // else: !if(wb_rst_i)
+
+ assign wb_dat_o = internal_reg;
+ assign port_output = internal_reg;
+ assign wb_ack_o = wb_stb_i;
+
+endmodule // wb_output_pins32
+