diff options
author | jcorgan <jcorgan@221aa14e-8319-0410-a670-987f0aec2ac5> | 2008-09-08 01:00:12 +0000 |
---|---|---|
committer | jcorgan <jcorgan@221aa14e-8319-0410-a670-987f0aec2ac5> | 2008-09-08 01:00:12 +0000 |
commit | 61f2f0214c5999ea42a368a4fc99f03d8eb28d1e (patch) | |
tree | e7e24a9adc05ff1422fe3ada9926a51634741b47 /control_lib/system_control.v | |
download | uhd-61f2f0214c5999ea42a368a4fc99f03d8eb28d1e.tar.gz uhd-61f2f0214c5999ea42a368a4fc99f03d8eb28d1e.tar.bz2 uhd-61f2f0214c5999ea42a368a4fc99f03d8eb28d1e.zip |
Merged r9433:9527 from features/gr-usrp2 into trunk. Adds usrp2 and gr-usrp2 top-level components. Trunk passes distcheck with mb-gcc installed, but currently not without them. The key issue is that when mb-gcc is not installed, the build system skips over the usrp2/firmware directory, and the firmware include files don't get put into the dist tarball. But we can't do the usual DIST_SUBDIRS method as the firmware is a subpackage.
git-svn-id: http://gnuradio.org/svn/gnuradio/trunk@9528 221aa14e-8319-0410-a670-987f0aec2ac5
Diffstat (limited to 'control_lib/system_control.v')
-rw-r--r-- | control_lib/system_control.v | 47 |
1 files changed, 47 insertions, 0 deletions
diff --git a/control_lib/system_control.v b/control_lib/system_control.v new file mode 100644 index 000000000..5d89f13db --- /dev/null +++ b/control_lib/system_control.v @@ -0,0 +1,47 @@ +// System bootup order: +// 0 - Internal POR to reset this block. Maybe control it from CPLD in the future? +// 1 - Everything in reset +// 2 - Take RAM Loader out of reset +// 3 - When RAM Loader done, take processor and wishbone out of reset + +module system_control + (input wb_clk_i, + output reg ram_loader_rst_o, + output reg wb_rst_o, + input ram_loader_done_i + ); + + reg POR = 1'b1; + reg [3:0] POR_ctr; + + initial POR_ctr = 4'd0; + always @(posedge wb_clk_i) + if(POR_ctr == 4'd15) + POR <= 1'b0; + else + POR_ctr <= POR_ctr + 4'd1; + + always @(posedge POR or posedge wb_clk_i) + if(POR) + ram_loader_rst_o <= 1'b1; + else + ram_loader_rst_o <= #1 1'b0; + + // Main system reset + reg delayed_rst; + + always @(posedge POR or posedge wb_clk_i) + if(POR) + begin + wb_rst_o <= 1'b1; + delayed_rst <= 1'b1; + end + else if(ram_loader_done_i) + begin + delayed_rst <= 1'b0; + wb_rst_o <= delayed_rst; + end + +endmodule // system_control + + |