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| author | Josh Blum <josh@joshknows.com> | 2010-01-22 16:00:45 -0800 |
|---|---|---|
| committer | Josh Blum <josh@joshknows.com> | 2010-01-22 16:00:45 -0800 |
| commit | 8b377a9d6d0ad281474a8dbff49ea3b093178b28 (patch) | |
| tree | 8e3c7a1b60f96df6e2140666d3b7afa5166d885d /control_lib/srl.v | |
| parent | e92d36dcfe02afaedec348f2d8fc4523fb4e633b (diff) | |
| download | uhd-8b377a9d6d0ad281474a8dbff49ea3b093178b28.tar.gz uhd-8b377a9d6d0ad281474a8dbff49ea3b093178b28.tar.bz2 uhd-8b377a9d6d0ad281474a8dbff49ea3b093178b28.zip | |
moved into subdir
Diffstat (limited to 'control_lib/srl.v')
| -rw-r--r-- | control_lib/srl.v | 21 |
1 files changed, 0 insertions, 21 deletions
diff --git a/control_lib/srl.v b/control_lib/srl.v deleted file mode 100644 index fa28c7669..000000000 --- a/control_lib/srl.v +++ /dev/null @@ -1,21 +0,0 @@ - -module srl - #(parameter WIDTH=18) - (input clk, - input write, - input [WIDTH-1:0] in, - input [3:0] addr, - output [WIDTH-1:0] out); - - genvar i; - generate - for (i=0;i<WIDTH;i=i+1) - begin : gen_srl - SRL16E - srl16e(.Q(out[i]), - .A0(addr[0]),.A1(addr[1]),.A2(addr[2]),.A3(addr[3]), - .CE(write),.CLK(clk),.D(in[i])); - end - endgenerate - -endmodule // srl |