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| author | Josh Blum <josh@joshknows.com> | 2010-01-22 11:56:55 -0800 |
|---|---|---|
| committer | Josh Blum <josh@joshknows.com> | 2010-01-22 11:56:55 -0800 |
| commit | 7bf8a6df381a667134b55701993c6770d32bc76b (patch) | |
| tree | 4a298fb5450f7277b5aaf5210740ae18f818c9aa /control_lib/srl.v | |
| parent | 8f2c33eab9396185df259639082b7d1618585973 (diff) | |
| download | uhd-7bf8a6df381a667134b55701993c6770d32bc76b.tar.gz uhd-7bf8a6df381a667134b55701993c6770d32bc76b.tar.bz2 uhd-7bf8a6df381a667134b55701993c6770d32bc76b.zip | |
Moved usrp2 fpga files into usrp2 subdir.
Diffstat (limited to 'control_lib/srl.v')
| -rw-r--r-- | control_lib/srl.v | 21 |
1 files changed, 0 insertions, 21 deletions
diff --git a/control_lib/srl.v b/control_lib/srl.v deleted file mode 100644 index fa28c7669..000000000 --- a/control_lib/srl.v +++ /dev/null @@ -1,21 +0,0 @@ - -module srl - #(parameter WIDTH=18) - (input clk, - input write, - input [WIDTH-1:0] in, - input [3:0] addr, - output [WIDTH-1:0] out); - - genvar i; - generate - for (i=0;i<WIDTH;i=i+1) - begin : gen_srl - SRL16E - srl16e(.Q(out[i]), - .A0(addr[0]),.A1(addr[1]),.A2(addr[2]),.A3(addr[3]), - .CE(write),.CLK(clk),.D(in[i])); - end - endgenerate - -endmodule // srl |