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authorjcorgan <jcorgan@221aa14e-8319-0410-a670-987f0aec2ac5>2008-09-08 01:00:12 +0000
committerjcorgan <jcorgan@221aa14e-8319-0410-a670-987f0aec2ac5>2008-09-08 01:00:12 +0000
commit61f2f0214c5999ea42a368a4fc99f03d8eb28d1e (patch)
treee7e24a9adc05ff1422fe3ada9926a51634741b47 /control_lib/simple_uart_rx.v
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Merged r9433:9527 from features/gr-usrp2 into trunk. Adds usrp2 and gr-usrp2 top-level components. Trunk passes distcheck with mb-gcc installed, but currently not without them. The key issue is that when mb-gcc is not installed, the build system skips over the usrp2/firmware directory, and the firmware include files don't get put into the dist tarball. But we can't do the usual DIST_SUBDIRS method as the firmware is a subpackage.
git-svn-id: http://gnuradio.org/svn/gnuradio/trunk@9528 221aa14e-8319-0410-a670-987f0aec2ac5
Diffstat (limited to 'control_lib/simple_uart_rx.v')
-rw-r--r--control_lib/simple_uart_rx.v64
1 files changed, 64 insertions, 0 deletions
diff --git a/control_lib/simple_uart_rx.v b/control_lib/simple_uart_rx.v
new file mode 100644
index 000000000..debdd618b
--- /dev/null
+++ b/control_lib/simple_uart_rx.v
@@ -0,0 +1,64 @@
+
+
+module simple_uart_rx
+ #(parameter DEPTH=0)
+ (input clk, input rst,
+ output [7:0] fifo_out, input fifo_read, output [7:0] fifo_level, output fifo_empty,
+ input [15:0] clkdiv, input rx);
+
+ reg rx_d1, rx_d2;
+ always @(posedge clk)
+ if(rst)
+ {rx_d2,rx_d1} <= 0;
+ else
+ {rx_d2,rx_d1} <= {rx_d1,rx};
+
+ reg [15:0] baud_ctr;
+ reg [3:0] bit_ctr;
+ reg [7:0] sr;
+
+ wire neg_trans = rx_d2 & ~rx_d1;
+ wire shift_now = baud_ctr == (clkdiv>>1);
+ wire stop_now = (bit_ctr == 10) && shift_now;
+ wire go_now = (bit_ctr == 0) && neg_trans;
+
+ always @(posedge clk)
+ if(rst)
+ sr <= 0;
+ else if(shift_now)
+ sr <= {rx_d2,sr[7:1]};
+
+ always @(posedge clk)
+ if(rst)
+ baud_ctr <= 0;
+ else
+ if(go_now)
+ baud_ctr <= 1;
+ else if(stop_now)
+ baud_ctr <= 0;
+ else if(baud_ctr >= clkdiv)
+ baud_ctr <= 1;
+ else if(baud_ctr != 0)
+ baud_ctr <= baud_ctr + 1;
+
+ always @(posedge clk)
+ if(rst)
+ bit_ctr <= 0;
+ else
+ if(go_now)
+ bit_ctr <= 1;
+ else if(stop_now)
+ bit_ctr <= 0;
+ else if(baud_ctr == clkdiv)
+ bit_ctr <= bit_ctr + 1;
+
+ wire full;
+ wire write = ~full & rx_d2 & stop_now;
+
+ medfifo #(.WIDTH(8),.DEPTH(DEPTH)) fifo
+ (.clk(clk),.rst(rst),
+ .datain(sr),.write(write),.full(full),
+ .dataout(fifo_out),.read(fifo_read),.empty(fifo_empty),
+ .clear(0),.space(),.occupied(fifo_level) );
+
+endmodule // simple_uart_rx