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author | Josh Blum <josh@joshknows.com> | 2010-01-22 16:00:45 -0800 |
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committer | Josh Blum <josh@joshknows.com> | 2010-01-22 16:00:45 -0800 |
commit | 8b377a9d6d0ad281474a8dbff49ea3b093178b28 (patch) | |
tree | 8e3c7a1b60f96df6e2140666d3b7afa5166d885d /control_lib/settings_bus.v | |
parent | e92d36dcfe02afaedec348f2d8fc4523fb4e633b (diff) | |
download | uhd-8b377a9d6d0ad281474a8dbff49ea3b093178b28.tar.gz uhd-8b377a9d6d0ad281474a8dbff49ea3b093178b28.tar.bz2 uhd-8b377a9d6d0ad281474a8dbff49ea3b093178b28.zip |
moved into subdir
Diffstat (limited to 'control_lib/settings_bus.v')
-rw-r--r-- | control_lib/settings_bus.v | 49 |
1 files changed, 0 insertions, 49 deletions
diff --git a/control_lib/settings_bus.v b/control_lib/settings_bus.v deleted file mode 100644 index d01a30ab4..000000000 --- a/control_lib/settings_bus.v +++ /dev/null @@ -1,49 +0,0 @@ - -// Grab settings off the wishbone bus, send them out to our simpler bus on the fast clock - -module settings_bus - #(parameter AWIDTH=16, parameter DWIDTH=32) - (input wb_clk, - input wb_rst, - input [AWIDTH-1:0] wb_adr_i, - input [DWIDTH-1:0] wb_dat_i, - input wb_stb_i, - input wb_we_i, - output reg wb_ack_o, - input sys_clk, - output strobe, - output reg [7:0] addr, - output reg [31:0] data); - - reg stb_int, stb_int_d1; - - always @(posedge wb_clk) - if(wb_rst) - begin - stb_int <= 1'b0; - addr <= 8'd0; - data <= 32'd0; - end - else if(wb_we_i & wb_stb_i) - begin - stb_int <= 1'b1; - addr <= wb_adr_i[9:2]; - data <= wb_dat_i; - end - else - stb_int <= 1'b0; - - always @(posedge wb_clk) - if(wb_rst) - wb_ack_o <= 0; - else - wb_ack_o <= wb_stb_i & ~wb_ack_o; - - always @(posedge wb_clk) - stb_int_d1 <= stb_int; - - //assign strobe = stb_int & ~stb_int_d1; - assign strobe = stb_int & wb_ack_o; - -endmodule // settings_bus - |