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author | Josh Blum <josh@joshknows.com> | 2010-01-22 11:56:55 -0800 |
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committer | Josh Blum <josh@joshknows.com> | 2010-01-22 11:56:55 -0800 |
commit | 7bf8a6df381a667134b55701993c6770d32bc76b (patch) | |
tree | 4a298fb5450f7277b5aaf5210740ae18f818c9aa /control_lib/setting_reg.v | |
parent | 8f2c33eab9396185df259639082b7d1618585973 (diff) | |
download | uhd-7bf8a6df381a667134b55701993c6770d32bc76b.tar.gz uhd-7bf8a6df381a667134b55701993c6770d32bc76b.tar.bz2 uhd-7bf8a6df381a667134b55701993c6770d32bc76b.zip |
Moved usrp2 fpga files into usrp2 subdir.
Diffstat (limited to 'control_lib/setting_reg.v')
-rw-r--r-- | control_lib/setting_reg.v | 23 |
1 files changed, 0 insertions, 23 deletions
diff --git a/control_lib/setting_reg.v b/control_lib/setting_reg.v deleted file mode 100644 index ccbaa3d2e..000000000 --- a/control_lib/setting_reg.v +++ /dev/null @@ -1,23 +0,0 @@ - - -module setting_reg - #(parameter my_addr = 0) - (input clk, input rst, input strobe, input wire [7:0] addr, - input wire [31:0] in, output reg [31:0] out, output reg changed); - - always @(posedge clk) - if(rst) - begin - out <= 32'd0; - changed <= 1'b0; - end - else - if(strobe & (my_addr==addr)) - begin - out <= in; - changed <= 1'b1; - end - else - changed <= 1'b0; - -endmodule // setting_reg |