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author | Josh Blum <josh@joshknows.com> | 2010-01-22 11:56:55 -0800 |
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committer | Josh Blum <josh@joshknows.com> | 2010-01-22 11:56:55 -0800 |
commit | 7bf8a6df381a667134b55701993c6770d32bc76b (patch) | |
tree | 4a298fb5450f7277b5aaf5210740ae18f818c9aa /control_lib/sd_spi_tb.v | |
parent | 8f2c33eab9396185df259639082b7d1618585973 (diff) | |
download | uhd-7bf8a6df381a667134b55701993c6770d32bc76b.tar.gz uhd-7bf8a6df381a667134b55701993c6770d32bc76b.tar.bz2 uhd-7bf8a6df381a667134b55701993c6770d32bc76b.zip |
Moved usrp2 fpga files into usrp2 subdir.
Diffstat (limited to 'control_lib/sd_spi_tb.v')
-rw-r--r-- | control_lib/sd_spi_tb.v | 40 |
1 files changed, 0 insertions, 40 deletions
diff --git a/control_lib/sd_spi_tb.v b/control_lib/sd_spi_tb.v deleted file mode 100644 index e30a5bdf6..000000000 --- a/control_lib/sd_spi_tb.v +++ /dev/null @@ -1,40 +0,0 @@ - - -module sd_spi_tb; - - reg clk = 0; - always #5 clk = ~clk; - reg rst = 1; - initial #32 rst = 0; - - wire sd_clk, sd_mosi, sd_miso; - wire [7:0] clk_div = 12; - wire [7:0] send_dat = 23; - wire [7:0] rcv_dat; - - wire ready; - reg go = 0; - initial - begin - repeat (100) - @(posedge clk); - go <= 1; - @(posedge clk); - go <= 0; - end - - sd_spi dut(.clk(clk),.rst(rst), - .sd_clk(sd_clk),.sd_mosi(sd_mosi),.sd_miso(sd_miso), - .clk_div(clk_div),.send_dat(send_dat),.rcv_dat(rcv_dat), - .go(go),.ready(ready) ); - - initial - begin - $dumpfile("sd_spi_tb.vcd"); - $dumpvars(0,sd_spi_tb); - end - - initial - #10000 $finish(); - -endmodule // sd_spi_tb |