Moved usrp2 fpga files into usrp2 subdir.

1 files changed, 0 insertions, 16 deletions

diff --git a/control_lib/reset_sync.v b/control_lib/reset_sync.v
deleted file mode 100644
index 94d966840..000000000
--- a/control_lib/reset_sync.v
+++ /dev/null
@@ -1,16 +0,0 @@
-
-
-module reset_sync
-  (input clk,
-   input reset_in,
-   output reg reset_out);
-
-   reg 	      reset_int;
-
-   always @(posedge clk or posedge reset_in)
-     if(reset_in)
-       {reset_out,reset_int} <= 2'b11;
-     else
-       {reset_out,reset_int} <= {reset_int,1'b0};
-   
-endmodule // reset_sync