new fifos copied over from other project

git-svn-id: http://gnuradio.org/svn/gnuradio/trunk@10709 221aa14e-8319-0410-a670-987f0aec2ac5

17 files changed, 6741 insertions, 0 deletions

diff --git a/control_lib/newfifo/fifo18_to_ll8.v b/control_lib/newfifo/fifo18_to_ll8.v
new file mode 100644
index 000000000..4653244ef
--- /dev/null
+++ b/control_lib/newfifo/fifo18_to_ll8.v
@@ -0,0 +1,58 @@
+
+module fifo18_to_ll8
+  (input clk, input reset, input clear,
+   input [35:0] f18_data,
+   input f18_src_rdy_i,
+   output f18_dst_rdy_o,
+
+   output reg [7:0] ll_data,
+   output ll_sof_n,
+   output ll_eof_n,
+   output ll_src_rdy_n,
+   input ll_dst_rdy_n);
+
+   wire  ll_sof, ll_eof, ll_src_rdy;
+   assign ll_sof_n = ~ll_sof;
+   assign ll_eof_n = ~ll_eof;
+   assign ll_src_rdy_n = ~ll_src_rdy;
+   wire ll_dst_rdy = ~ll_dst_rdy_n;
+
+   wire   f18_sof = f18_data[32];
+   wire   f18_eof = f18_data[33];
+   wire   f18_occ = f18_data[35:34];
+   wire advance, end_early;
+   reg [1:0] state;
+   assign debug    = {29'b0,state};
+
+   always @(posedge clk)
+     if(reset)
+       state 	  <= 0;
+     else
+       if(advance)
+	 if(ll_eof)
+	   state  <= 0;
+	 else
+	   state  <= state + 1;
+
+   always @*
+     case(state)
+       0 : ll_data = f18_data[31:24];
+       1 : ll_data = f18_data[23:16];
+       2 : ll_data = f18_data[15:8];
+       3 : ll_data = f18_data[7:0];
+       default : ll_data = f18_data[31:24];
+       endcase // case (state)
+   
+   assign ll_sof 	 = (state==0) & f18_sof;
+   assign ll_eof 	 = f18_eof & (((state==0)&(f18_occ==1)) |
+			       ((state==1)&(f18_occ==2)) |
+			       ((state==2)&(f18_occ==3)) |
+			       (state==3));
+   
+   assign ll_src_rdy 	 = f18_src_rdy_i;
+
+   assign advance 	 = ll_src_rdy & ll_dst_rdy;
+   assign f18_dst_rdy_o  = advance & ((state==3)|ll_eof);
+   assign debug 	 = state;
+   
+endmodule // ll8_to_fifo36
diff --git a/control_lib/newfifo/fifo19_to_fifo36.v b/control_lib/newfifo/fifo19_to_fifo36.v
new file mode 100644
index 000000000..e22ca0a49
--- /dev/null
+++ b/control_lib/newfifo/fifo19_to_fifo36.v
@@ -0,0 +1,71 @@
+
+module fifo19_to_fifo36
+  (input clk, input reset, input clear,
+   input [18:0] f19_datain,
+   input f19_src_rdy_i,
+   output f19_dst_rdy_o,
+
+   output [35:0] f36_dataout,
+   output f36_src_rdy_o,
+   input f36_dst_rdy_i
+   );
+
+   reg 	 f36_sof, f36_eof, f36_occ;
+   
+   reg [1:0] state;
+   reg [15:0] dat0, dat1;
+
+   wire f19_sof  = f19_datain[16];
+   wire f19_eof  = f19_datain[17];
+   wire f19_occ  = f19_datain[18];
+
+   wire xfer_out = f36_src_rdy_o & f36_dst_rdy_i;
+
+   always @(posedge clk)
+     if(f19_src_rdy_i & ((state==0)|xfer_out))
+       f36_sof 	<= f19_sof;
+
+   always @(posedge clk)
+     if(f19_src_rdy_i & ((state != 2)|xfer_out))
+       f36_eof 	<= f19_eof;
+
+   always @(posedge clk)    // FIXME check this
+     if(f19_eof)
+       f36_occ 	<= {state[0],f19_occ};
+     else
+       f36_occ 	<= 0;
+   
+   always @(posedge clk)
+     if(reset)
+       state 	<= 0;
+     else
+       if(f19_src_rdy_i)
+	 case(state)
+	   0 : 
+	     if(f19_eof)
+	       state <= 2;
+	     else
+	       state <= 1;
+	   1 : 
+	     state <= 2;
+	   2 : 
+	     if(xfer_out)
+	       state 	   <= 1;
+	 endcase // case(state)
+       else
+	 if(xfer_out)
+	   state 	   <= 0;
+
+   always @(posedge clk)
+     if(f19_src_rdy_i & (state==1))
+       dat1 		   <= f19_datain;
+
+   always @(posedge clk)
+     if(f19_src_rdy_i & ((state==0) | xfer_out))
+       dat0 		   <= f19_datain;
+   
+   assign    f19_dst_rdy_o  = xfer_out | (state != 2);
+   assign    f36_dataout    = {f36_occ,f36_eof,f36_sof,dat0,dat1};
+   assign    f36_src_rdy_o  = (state == 2);
+      
+endmodule // fifo19_to_fifo36
diff --git a/control_lib/newfifo/fifo19_to_ll8.v b/control_lib/newfifo/fifo19_to_ll8.v
new file mode 100644
index 000000000..4707f7523
--- /dev/null
+++ b/control_lib/newfifo/fifo19_to_ll8.v
@@ -0,0 +1,53 @@
+
+module fifo19_to_ll8
+  (input clk, input reset, input clear,
+   input [18:0] f19_data,
+   input f19_src_rdy_i,
+   output f19_dst_rdy_o,
+
+   output reg [7:0] ll_data,
+   output ll_sof_n,
+   output ll_eof_n,
+   output ll_src_rdy_n,
+   input ll_dst_rdy_n);
+
+   wire  ll_sof, ll_eof, ll_src_rdy;
+   assign ll_sof_n 	= ~ll_sof;
+   assign ll_eof_n 	= ~ll_eof;
+   assign ll_src_rdy_n 	= ~ll_src_rdy;
+   wire ll_dst_rdy 	= ~ll_dst_rdy_n;
+
+   wire   f19_sof 	= f19_data[16];
+   wire   f19_eof 	= f19_data[17];
+   wire   f19_occ 	= f19_data[18];
+   
+   wire advance, end_early;
+   reg state;
+
+   always @(posedge clk)
+     if(reset)
+       state 	  <= 0;
+     else
+       if(advance)
+	 if(ll_eof)
+	   state  <= 0;
+	 else
+	   state  <= state + 1;
+
+   always @*
+     case(state)
+       0 : ll_data = f19_data[15:8];
+       1 : ll_data = f19_data[7:0];
+       default : ll_data = f19_data[15:8];
+       endcase // case (state)
+   
+   assign ll_sof 	 = (state==0) & f19_sof;
+   assign ll_eof 	 = f19_eof & ((f19_occ==1)|(state==1));
+   
+   assign ll_src_rdy 	 = f19_src_rdy_i;
+
+   assign advance 	 = ll_src_rdy & ll_dst_rdy;
+   assign f19_dst_rdy_o  = advance & ((state==1)|ll_eof);
+   
+endmodule // fifo19_to_ll8
+
diff --git a/control_lib/newfifo/fifo36_to_fifo18.v b/control_lib/newfifo/fifo36_to_fifo18.v
new file mode 100644
index 000000000..b636ab9ca
--- /dev/null
+++ b/control_lib/newfifo/fifo36_to_fifo18.v
@@ -0,0 +1,40 @@
+
+module fifo36_to_fifo18
+  (input clk, input reset, input clear,
+   input [35:0] f36_datain,
+   input f36_src_rdy_i,
+   output f36_dst_rdy_o,
+   
+   output [17:0] f18_dataout,
+   output f18_src_rdy_o,
+   input f18_dst_rdy_i );
+
+   wire   f36_sof  = f36_datain[32];
+   wire   f36_eof  = f36_datain[33];
+   wire   f36_occ  = f36_datain[35:34];
+
+   reg phase;
+
+   wire half_line 	   = f36_eof & ((f36_occ==1)|(f36_occ==2));
+   
+   assign f18_dataout[15:0] = phase ? f36_datain[15:0] : f36_datain[31:16];
+   assign f18_dataout[16]  = phase ? 0 : f36_sof;
+   assign f18_dataout[17]  = phase ? f36_eof : half_line;
+   
+   assign f18_src_rdy_o    = f36_src_rdy_i;
+   assign f36_dst_rdy_o    = (phase | half_line) & f18_dst_rdy_i;
+	
+   wire f18_xfer 	   = f18_src_rdy_o & f18_dst_rdy_i;
+   wire f36_xfer 	   = f36_src_rdy_i & f36_dst_rdy_o;
+
+   always @(posedge clk)
+     if(reset)
+       phase 		  <= 0;
+     else if(f36_xfer)
+       phase 		  <= 0;
+     else if(f18_xfer)
+       phase 		  <= 1;
+   
+       
+endmodule // fifo36_to_fifo18
+
diff --git a/control_lib/newfifo/fifo36_to_fifo19.v b/control_lib/newfifo/fifo36_to_fifo19.v
new file mode 100644
index 000000000..de249aaeb
--- /dev/null
+++ b/control_lib/newfifo/fifo36_to_fifo19.v
@@ -0,0 +1,41 @@
+
+module fifo36_to_fifo19
+  (input clk, input reset, input clear,
+   input [35:0] f36_datain,
+   input f36_src_rdy_i,
+   output f36_dst_rdy_o,
+   
+   output [18:0] f19_dataout,
+   output f19_src_rdy_o,
+   input f19_dst_rdy_i );
+
+   wire   f36_sof  = f36_datain[32];
+   wire   f36_eof  = f36_datain[33];
+   wire   f36_occ  = f36_datain[35:34];
+
+   reg phase;
+
+   wire half_line 	   = f36_eof & ((f36_occ==1)|(f36_occ==2));
+   
+   assign f19_dataout[15:0] = phase ? f36_datain[15:0] : f36_datain[31:16];
+   assign f19_dataout[16]  = phase ? 0 : f36_sof;
+   assign f19_dataout[17]  = phase ? f36_eof : half_line;
+   assign f19_dataout[18]  = f19_dataout[17] & ((f36_occ==1)|(f36_occ==3));
+   
+   assign f19_src_rdy_o    = f36_src_rdy_i;
+   assign f36_dst_rdy_o    = (phase | half_line) & f19_dst_rdy_i;
+	
+   wire f19_xfer 	   = f19_src_rdy_o & f19_dst_rdy_i;
+   wire f36_xfer 	   = f36_src_rdy_i & f36_dst_rdy_o;
+
+   always @(posedge clk)
+     if(reset)
+       phase 		  <= 0;
+     else if(f36_xfer)
+       phase 		  <= 0;
+     else if(f19_xfer)
+       phase 		  <= 1;
+   
+       
+endmodule // fifo36_to_fifo19
+
diff --git a/control_lib/newfifo/fifo36_to_ll8.v b/control_lib/newfifo/fifo36_to_ll8.v
new file mode 100644
index 000000000..1befb9e6e
--- /dev/null
+++ b/control_lib/newfifo/fifo36_to_ll8.v
@@ -0,0 +1,60 @@
+
+module fifo36_to_ll8
+  (input clk, reset,
+   input [35:0] f36_data,
+   input f36_src_rdy_i,
+   output f36_dst_rdy_o,
+
+   output reg [7:0] ll_data,
+   output ll_sof_n,
+   output ll_eof_n,
+   output ll_src_rdy_n,
+   input ll_dst_rdy_n,
+
+   output [31:0] debug);
+
+   wire  ll_sof, ll_eof, ll_src_rdy;
+   assign ll_sof_n = ~ll_sof;
+   assign ll_eof_n = ~ll_eof;
+   assign ll_src_rdy_n = ~ll_src_rdy;
+   wire ll_dst_rdy = ~ll_dst_rdy_n;
+
+   wire   f36_sof = f36_data[32];
+   wire   f36_eof = f36_data[33];
+   wire   f36_occ = f36_data[35:34];
+   wire advance, end_early;
+   reg [1:0] state;
+   assign debug    = {29'b0,state};
+
+   always @(posedge clk)
+     if(reset)
+       state 	  <= 0;
+     else
+       if(advance)
+	 if(ll_eof)
+	   state  <= 0;
+	 else
+	   state  <= state + 1;
+
+   always @*
+     case(state)
+       0 : ll_data = f36_data[31:24];
+       1 : ll_data = f36_data[23:16];
+       2 : ll_data = f36_data[15:8];
+       3 : ll_data = f36_data[7:0];
+       default : ll_data = f36_data[31:24];
+       endcase // case (state)
+   
+   assign ll_sof 	 = (state==0) & f36_sof;
+   assign ll_eof 	 = f36_eof & (((state==0)&(f36_occ==1)) |
+			       ((state==1)&(f36_occ==2)) |
+			       ((state==2)&(f36_occ==3)) |
+			       (state==3));
+   
+   assign ll_src_rdy 	 = f36_src_rdy_i;
+
+   assign advance 	 = ll_src_rdy & ll_dst_rdy;
+   assign f36_dst_rdy_o  = advance & ((state==3)|ll_eof);
+   assign debug 	 = state;
+   
+endmodule // ll8_to_fifo36
diff --git a/control_lib/newfifo/fifo_2clock.v b/control_lib/newfifo/fifo_2clock.v
new file mode 100644
index 000000000..6b1eb607e
--- /dev/null
+++ b/control_lib/newfifo/fifo_2clock.v
@@ -0,0 +1,66 @@
+
+module fifo_2clock
+  #(parameter DWIDTH=32, AWIDTH=9)
+    (input wclk, input [DWIDTH-1:0] datain, input write, output full, output reg [AWIDTH-1:0] level_wclk,
+     input rclk, output [DWIDTH-1:0] dataout, input read, output empty, output reg [AWIDTH-1:0] level_rclk,
+     input arst);
+
+   reg [AWIDTH-1:0] wr_addr, rd_addr;
+   wire [AWIDTH-1:0] wr_addr_rclk, rd_addr_wclk;
+   wire [AWIDTH-1:0] next_rd_addr;
+   wire 	    enb_read;
+   
+   // Write side management
+   wire [AWIDTH-1:0] next_wr_addr = wr_addr + 1;
+   always @(posedge wclk or posedge arst)
+     if(arst)
+       wr_addr <= 0;
+     else if(write)
+       wr_addr <= next_wr_addr;
+   assign 	    full = (next_wr_addr == rd_addr_wclk);
+
+   //  RAM for data storage.  Data out is registered, complicating the
+   //     read side logic
+   ram_2port #(.DWIDTH(DWIDTH),.AWIDTH(AWIDTH)) mac_rx_ff_ram
+     (.clka(wclk),.ena(1'b1),.wea(write),.addra(wr_addr),.dia(datain),.doa(),
+      .clkb(rclk),.enb(enb_read),.web(1'b0),.addrb(next_rd_addr),.dib(0),.dob(dataout) );
+
+   // Read side management
+   reg 		    data_valid;
+   assign 	    empty = ~data_valid;
+   assign 	    next_rd_addr = rd_addr + data_valid;
+   assign 	    enb_read = read | ~data_valid;
+
+   always @(posedge rclk or posedge arst)
+     if(arst)
+       rd_addr <= 0;
+     else if(read)
+       rd_addr <= rd_addr + 1;
+
+   always @(posedge rclk or posedge arst)
+     if(arst)
+       data_valid <= 0;
+     else
+       if(read & (next_rd_addr == wr_addr_rclk))
+	 data_valid <= 0;
+       else if(next_rd_addr != wr_addr_rclk)
+	 data_valid <= 1;
+	 
+   // Send pointers across clock domains via gray code
+   gray_send #(.WIDTH(AWIDTH)) send_wr_addr
+     (.clk_in(wclk),.addr_in(wr_addr),
+      .clk_out(rclk),.addr_out(wr_addr_rclk) );
+   
+   gray_send #(.WIDTH(AWIDTH)) send_rd_addr
+     (.clk_in(rclk),.addr_in(rd_addr),
+      .clk_out(wclk),.addr_out(rd_addr_wclk) );
+
+   // Generate fullness info, these are approximate and may be delayed 
+   // and are only for higher-level flow control.  
+   // Only full and empty are guaranteed exact.
+   always @(posedge wclk) 
+     level_wclk <= wr_addr - rd_addr_wclk;
+   always @(posedge rclk) 
+     level_rclk <= wr_addr_rclk - rd_addr;
+   
+endmodule // fifo_2clock
diff --git a/control_lib/newfifo/fifo_2clock_casc.v b/control_lib/newfifo/fifo_2clock_casc.v
new file mode 100644
index 000000000..e9b0cfc25
--- /dev/null
+++ b/control_lib/newfifo/fifo_2clock_casc.v
@@ -0,0 +1,31 @@
+
+module fifo_2clock_casc
+  #(parameter DWIDTH=32, AWIDTH=9)
+    (input wclk, input [DWIDTH-1:0] datain, input write, output full, output [AWIDTH-1:0] level_wclk,
+     input rclk, output [DWIDTH-1:0] dataout, input read, output empty, output [AWIDTH-1:0] level_rclk,
+     input arst);
+
+   wire    full_int, empty_int, full_int2, empty_int2, transfer, transfer2;
+   wire [DWIDTH-1:0] data_int, data_int2;
+   
+   shortfifo #(.WIDTH(DWIDTH)) shortfifo
+     (.clk(wclk), .rst(arst), .clear(0),
+      .datain(datain), .write(write), .full(full),
+      .dataout(data_int), .read(transfer), .empty(empty_int) );
+
+   assign  transfer = ~full_int & ~empty_int;
+   
+   fifo_2clock #(.DWIDTH(DWIDTH),.AWIDTH(AWIDTH)) fifo_2clock
+     (.wclk(wclk), .datain(data_int), .write(transfer), .full(full_int), .level_wclk(level_wclk),
+      .rclk(rclk), .dataout(data_int2), .read(transfer2), .empty(empty_int2), .level_rclk(level_rclk),
+      .arst(arst) );
+
+   assign  transfer2 = ~full_int2 & ~empty_int2;
+
+   shortfifo #(.WIDTH(DWIDTH)) shortfifo2
+     (.clk(rclk), .rst(arst), .clear(0),
+      .datain(data_int2), .write(transfer2), .full(full_int2),
+      .dataout(dataout), .read(read), .empty(empty) );
+   
+endmodule // fifo_2clock_casc
+
diff --git a/control_lib/newfifo/fifo_cascade.v b/control_lib/newfifo/fifo_cascade.v
new file mode 100644
index 000000000..fdd8449bc
--- /dev/null
+++ b/control_lib/newfifo/fifo_cascade.v
@@ -0,0 +1,52 @@
+
+
+// This FIFO exists to provide an intermediate point for the data on its
+// long trek from one RAM (in the buffer pool) to another (in the longfifo)
+// The shortfifo is more flexible in its placement since it is based on
+// distributed RAM
+
+// This one has the shortfifo on both the in and out sides.
+module fifo_cascade
+  #(parameter WIDTH=32, SIZE=9)
+    (input clk, input reset, input clear,
+     input [WIDTH-1:0] datain,
+     input src_rdy_i,
+     output dst_rdy_o,
+     output [WIDTH-1:0] dataout,
+     output src_rdy_o,
+     input dst_rdy_i,
+     output [15:0] space,
+     output [15:0] occupied);
+
+   wire [WIDTH-1:0] data_int, data_int2;
+   wire src_rdy_1, dst_rdy_1, src_rdy_2, dst_rdy_2;
+   
+   wire [4:0] 	    s1_space, s1_occupied, s2_space, s2_occupied;
+   wire [15:0] 	    l_space, l_occupied;
+   
+   fifo_short #(.WIDTH(WIDTH)) head_fifo
+     (.clk(clk),.reset(reset),.clear(clear),
+      .datain(datain), .src_rdy_i(src_rdy_i), .dst_rdy_o(dst_rdy_o),
+      .dataout(data_int), .src_rdy_o(src_rdy_1), .dst_rdy_i(dst_rdy_1),
+      .space(s1_space),.occupied(s1_occupied) );
+      
+   fifo_long #(.WIDTH(WIDTH),.SIZE(SIZE)) middle_fifo
+     (.clk(clk),.reset(reset),.clear(clear),
+      .datain(data_int), .src_rdy_i(src_rdy_1), .dst_rdy_o(dst_rdy_1),
+      .dataout(data_int2), .src_rdy_o(src_rdy_2), .dst_rdy_i(dst_rdy_2),
+      .space(l_space),.occupied(l_occupied) );
+   
+   fifo_short #(.WIDTH(WIDTH)) tail_fifo
+     (.clk(clk),.reset(reset),.clear(clear),
+      .datain(data_int2), .src_rdy_i(src_rdy_2), .dst_rdy_o(dst_rdy_2),
+      .dataout(dataout), .src_rdy_o(src_rdy_o), .dst_rdy_i(dst_rdy_i),
+      .space(s2_space),.occupied(s2_occupied) );
+   
+   assign 	    space = {11'b0,s1_space} + {11'b0,s2_space} + l_space;
+   assign 	    occupied = {11'b0,s1_occupied} + {11'b0,s2_occupied} + l_occupied;
+      
+endmodule // cascadefifo2
+
+
+
+
diff --git a/control_lib/newfifo/fifo_long.v b/control_lib/newfifo/fifo_long.v
new file mode 100644
index 000000000..0426779f6
--- /dev/null
+++ b/control_lib/newfifo/fifo_long.v
@@ -0,0 +1,148 @@
+
+// FIFO intended to be interchangeable with shortfifo, but
+//  based on block ram instead of SRL16's
+//  only one clock domain
+
+// Port A is write port, Port B is read port
+
+module fifo_long
+  #(parameter WIDTH=32, SIZE=9)
+   (input clk, input reset, input clear,
+    input [WIDTH-1:0] datain,
+    input src_rdy_i,
+    output dst_rdy_o,
+    output [WIDTH-1:0] dataout,
+    output src_rdy_o,
+    input dst_rdy_i,
+    
+    output reg [15:0] space,
+    output reg [15:0] occupied);
+   
+   wire write 	     = src_rdy_i & dst_rdy_o;
+   wire read 	     = dst_rdy_i & src_rdy_o;
+   wire full, empty;
+   
+   assign dst_rdy_o  = ~full;
+   assign src_rdy_o  = ~empty;
+   
+   // Read side states
+   localparam 	  EMPTY = 0;
+   localparam 	  PRE_READ = 1;
+   localparam 	  READING = 2;
+
+   reg [SIZE-1:0] wr_addr, rd_addr;
+   reg [1:0] 	  read_state;
+
+   reg 	  empty_reg, full_reg;
+   always @(posedge clk)
+     if(reset)
+       wr_addr <= 0;
+     else if(clear)
+       wr_addr <= 0;
+     else if(write)
+       wr_addr <= wr_addr + 1;
+
+   ram_2port #(.DWIDTH(WIDTH),.AWIDTH(SIZE))
+     ram (.clka(clk),
+	  .ena(1'b1),
+	  .wea(write),
+	  .addra(wr_addr),
+	  .dia(datain),
+	  .doa(),
+
+	  .clkb(clk),
+	  .enb((read_state==PRE_READ)|read),
+	  .web(0),
+	  .addrb(rd_addr),
+	  .dib(0),
+	  .dob(dataout));
+
+   always @(posedge clk)
+     if(reset)
+       begin
+	  read_state <= EMPTY;
+	  rd_addr <= 0;
+	  empty_reg <= 1;
+       end
+     else
+       if(clear)
+	 begin
+	    read_state <= EMPTY;
+	    rd_addr <= 0;
+	    empty_reg <= 1;
+	 end
+       else 
+	 case(read_state)
+	   EMPTY :
+	     if(write)
+	       begin
+		  //rd_addr <= wr_addr;
+		  read_state <= PRE_READ;
+	       end
+	   PRE_READ :
+	     begin
+		read_state <= READING;
+		empty_reg <= 0;
+		rd_addr <= rd_addr + 1;
+	     end
+	   
+	   READING :
+	     if(read)
+	       if(rd_addr == wr_addr)
+		 begin
+		    empty_reg <= 1;
+		    if(write)
+		      read_state <= PRE_READ;
+		    else
+		      read_state <= EMPTY;
+		 end
+	       else
+		 rd_addr <= rd_addr + 1;
+	 endcase // case(read_state)
+
+   wire [SIZE-1:0] dont_write_past_me = rd_addr - 3;
+   wire 	   becoming_full = wr_addr == dont_write_past_me;
+     
+   always @(posedge clk)
+     if(reset)
+       full_reg <= 0;
+     else if(clear)
+       full_reg <= 0;
+     else if(read & ~write)
+       full_reg <= 0;
+     //else if(write & ~read & (wr_addr == (rd_addr-3)))
+     else if(write & ~read & becoming_full)
+       full_reg <= 1;
+
+   //assign empty = (read_state != READING);
+   assign empty = empty_reg;
+
+   // assign full = ((rd_addr - 1) == wr_addr);
+   assign full = full_reg;
+
+   //////////////////////////////////////////////
+   // space and occupied are for diagnostics only
+   // not guaranteed exact
+
+   localparam NUMLINES = (1<<SIZE)-2;
+   always @(posedge clk)
+     if(reset)
+       space <= NUMLINES;
+     else if(clear)
+       space <= NUMLINES;
+     else if(read & ~write)
+       space <= space + 1;
+     else if(write & ~read)
+       space <= space - 1;
+   
+   always @(posedge clk)
+     if(reset)
+       occupied <= 0;
+     else if(clear)
+       occupied <= 0;
+     else if(read & ~write)
+       occupied <= occupied - 1;
+     else if(write & ~read)
+       occupied <= occupied + 1;
+   
+endmodule // fifo_long
diff --git a/control_lib/newfifo/fifo_new_tb.v b/control_lib/newfifo/fifo_new_tb.v
new file mode 100644
index 000000000..f561df7fa
--- /dev/null
+++ b/control_lib/newfifo/fifo_new_tb.v
@@ -0,0 +1,158 @@
+module fifo_new_tb();
+   
+   reg clk = 0;
+   reg rst = 1;
+   reg clear = 0;
+   initial #1000 rst = 0;
+   always #50 clk = ~clk;
+   
+   reg [31:0] f36_data = 0;
+   reg [1:0] f36_occ = 0;
+   reg f36_sof = 0, f36_eof = 0;
+   
+   wire [35:0] f36_in = {f36_occ,f36_eof,f36_sof,f36_data};
+   reg src_rdy_f36i  = 0;
+   wire dst_rdy_f36i;
+
+   wire [35:0] f36_out, f36_out2;
+   wire src_rdy_f36o;
+   reg dst_rdy_f36o  = 0;
+   
+   //fifo_cascade #(.WIDTH(36), .SIZE(4)) fifo_cascade36
+   //fifo_long #(.WIDTH(36), .SIZE(4)) fifo_cascade36
+
+   wire i1_sr, i1_dr;
+   wire i2_sr, i2_dr;
+   wire i3_sr, i3_dr;
+   reg i4_dr = 0;
+   wire i4_sr;
+      
+   wire [35:0] i1, i4;
+   wire [18:0] i2, i3;
+   
+   wire [7:0] ll_data;
+   wire ll_src_rdy_n, ll_dst_rdy_n, ll_sof_n, ll_eof_n;
+   
+   fifo_short #(.WIDTH(36)) fifo_short1
+     (.clk(clk),.reset(rst),.clear(clear),
+      .datain(f36_in),.src_rdy_i(src_rdy_f36i),.dst_rdy_o(dst_rdy_f36i),
+      .dataout(i1),.src_rdy_o(i1_sr),.dst_rdy_i(i1_dr) );
+
+   fifo36_to_fifo19 fifo36_to_fifo19
+     (.clk(clk),.reset(rst),.clear(clear),
+      .f36_datain(i1),.f36_src_rdy_i(i1_sr),.f36_dst_rdy_o(i1_dr),
+      .f19_dataout(i2),.f19_src_rdy_o(i2_sr),.f19_dst_rdy_i(i2_dr) );
+
+   fifo19_to_ll8 fifo19_to_ll8
+     (.clk(clk),.reset(rst),.clear(clear),
+      .f19_data(i2),.f19_src_rdy_i(i2_sr),.f19_dst_rdy_o(i2_dr),
+      .ll_data(ll_data),.ll_sof_n(ll_sof_n),.ll_eof_n(ll_eof_n),
+      .ll_src_rdy_n(ll_src_rdy_n),.ll_dst_rdy_n(ll_dst_rdy_n));
+
+   ll8_to_fifo19 ll8_to_fifo19
+     (.clk(clk),.reset(rst),.clear(clear),
+      .ll_data(ll_data),.ll_sof_n(ll_sof_n),.ll_eof_n(ll_eof_n),
+      .ll_src_rdy_n(ll_src_rdy_n),.ll_dst_rdy_n(ll_dst_rdy_n),
+      .f19_data(i3),.f19_src_rdy_o(i3_sr),.f19_dst_rdy_i(i3_dr) );
+
+   fifo19_to_fifo36 fifo19_to_fifo36
+     (.clk(clk),.reset(rst),.clear(clear),
+      .f19_datain(i3),.f19_src_rdy_i(i3_sr),.f19_dst_rdy_o(i3_dr),
+      .f36_dataout(i4),.f36_src_rdy_o(i4_sr),.f36_dst_rdy_i(i4_dr) );
+     
+   task ReadFromFIFO36;
+      begin
+	 $display("Read from FIFO36");
+	 #1 i4_dr <= 1;
+	 while(1)
+	   begin
+	      while(~i4_sr)
+		@(posedge clk);
+	      $display("Read: %h",i4);
+	      @(posedge clk);
+	   end
+      end
+   endtask // ReadFromFIFO36
+
+   reg [15:0] count;
+   task PutPacketInFIFO36;
+      input [31:0] data_start;
+      input [31:0] data_len;
+      begin
+	 count 	      <= 4;
+	 src_rdy_f36i <= 1;
+	 f36_data     <= data_start;
+	 f36_sof      <= 1;
+	 f36_eof      <= 0;
+	 f36_occ      <= 0;
+	
+	 $display("Put Packet in FIFO36");
+	 while(~dst_rdy_f36i)
+	   @(posedge clk);
+	 @(posedge clk);
+	 $display("PPI_FIFO36: Entered First Line");
+	 f36_sof <= 0;
+	 while(count+4 < data_len)
+	   begin
+	      f36_data <= f36_data + 32'h01010101;
+	      count    <= count + 4;
+	      while(~dst_rdy_f36i)
+		@(posedge clk);
+	      @(posedge clk);
+	      $display("PPI_FIFO36: Entered New Line");
+	   end
+	 f36_data  <= f36_data + 32'h01010101;
+	 f36_eof   <= 1;
+	 if(count + 4 == data_len)
+	   f36_occ <= 0;
+	 else if(count + 3 == data_len)
+	   f36_occ <= 3;
+	 else if(count + 2 == data_len)
+	   f36_occ <= 2;
+	 else
+	   f36_occ <= 1;
+	 while(~dst_rdy_f36i)
+	   @(posedge clk);
+	 @(posedge clk);
+	 f36_occ      <= 0;
+	 f36_eof      <= 0;
+	 f36_data     <= 0;
+	 src_rdy_f36i <= 0;
+	 $display("PPI_FIFO36: Entered Last Line");
+      end
+   endtask // PutPacketInFIFO36
+   
+   initial $dumpfile("fifo_new_tb.vcd");
+   initial $dumpvars(0,fifo_new_tb);
+
+   initial
+     begin
+	@(negedge rst);
+	//#10000;
+	@(posedge clk);
+	@(posedge clk);
+	@(posedge clk);
+	@(posedge clk);
+	ReadFromFIFO36;
+     end
+   
+   initial
+     begin
+	@(negedge rst);
+	@(posedge clk);
+	@(posedge clk);
+	PutPacketInFIFO36(32'hA0B0C0D0,12);
+	@(posedge clk);
+	@(posedge clk);
+	#10000;
+	@(posedge clk);
+	PutPacketInFIFO36(32'hE0F0A0B0,36);
+	@(posedge clk);
+	@(posedge clk);
+	@(posedge clk);
+	@(posedge clk);
+	@(posedge clk);
+     end
+
+   initial #20000 $finish;
+endmodule // longfifo_tb
diff --git a/control_lib/newfifo/fifo_new_tb.vcd b/control_lib/newfifo/fifo_new_tb.vcd
new file mode 100644
index 000000000..796889e7d
--- /dev/null
+++ b/control_lib/newfifo/fifo_new_tb.vcd
@@ -0,0 +1,5506 @@
+$date
+	Thu Mar 19 17:21:11 2009
+$end
+$version
+	Icarus Verilog
+$end
+$timescale
+	1ps
+$end
+$scope module fifo_new_tb $end
+$var wire 1 ! dst_rdy_f36i $end
+$var wire 36 " f36_in [35:0] $end
+$var wire 36 # i1 [35:0] $end
+$var wire 1 $ i1_dr $end
+$var wire 1 % i1_sr $end
+$var wire 19 & i2 [18:0] $end
+$var wire 1 ' i2_dr $end
+$var wire 1 ( i2_sr $end
+$var wire 19 ) i3 [18:0] $end
+$var wire 1 * i3_dr $end
+$var wire 1 + i3_sr $end
+$var wire 36 , i4 [35:0] $end
+$var wire 1 - i4_sr $end
+$var wire 8 . ll_data [7:0] $end
+$var wire 1 / ll_dst_rdy_n $end
+$var wire 1 0 ll_eof_n $end
+$var wire 1 1 ll_sof_n $end
+$var wire 1 2 ll_src_rdy_n $end
+$var reg 1 3 clear $end
+$var reg 1 4 clk $end
+$var reg 16 5 count [15:0] $end
+$var reg 1 6 dst_rdy_f36o $end
+$var reg 32 7 f36_data [31:0] $end
+$var reg 1 8 f36_eof $end
+$var reg 2 9 f36_occ [1:0] $end
+$var reg 1 : f36_sof $end
+$var reg 1 ; i4_dr $end
+$var reg 1 < rst $end
+$var reg 1 = src_rdy_f36i $end
+$scope module fifo_short1 $end
+$var wire 1 > clear $end
+$var wire 1 ? clk $end
+$var wire 36 @ datain [35:0] $end
+$var wire 36 A dataout [35:0] $end
+$var wire 1 $ dst_rdy_i $end
+$var wire 1 ! dst_rdy_o $end
+$var wire 1 B read $end
+$var wire 1 C reset $end
+$var wire 1 D src_rdy_i $end
+$var wire 1 % src_rdy_o $end
+$var wire 1 E write $end
+$var reg 4 F a [3:0] $end
+$var reg 1 G empty $end
+$var reg 1 H full $end
+$var reg 5 I occupied [4:0] $end
+$var reg 5 J space [4:0] $end
+$scope begin gen_srl16[0] $end
+$scope module srl16e $end
+$var wire 1 K A0 $end
+$var wire 1 L A1 $end
+$var wire 1 M A2 $end
+$var wire 1 N A3 $end
+$var wire 1 E CE $end
+$var wire 1 ? CLK $end
+$var wire 1 O D $end
+$var wire 1 P Q $end
+$var reg 16 Q data [15:0] $end
+$upscope $end
+$upscope $end
+$scope begin gen_srl16[1] $end
+$scope module srl16e $end
+$var wire 1 R A0 $end
+$var wire 1 S A1 $end
+$var wire 1 T A2 $end
+$var wire 1 U A3 $end
+$var wire 1 E CE $end
+$var wire 1 ? CLK $end
+$var wire 1 V D $end
+$var wire 1 W Q $end
+$var reg 16 X data [15:0] $end
+$upscope $end
+$upscope $end
+$scope begin gen_srl16[2] $end
+$scope module srl16e $end
+$var wire 1 Y A0 $end
+$var wire 1 Z A1 $end
+$var wire 1 [ A2 $end
+$var wire 1 \ A3 $end
+$var wire 1 E CE $end
+$var wire 1 ? CLK $end
+$var wire 1 ] D $end
+$var wire 1 ^ Q $end
+$var reg 16 _ data [15:0] $end
+$upscope $end
+$upscope $end
+$scope begin gen_srl16[3] $end
+$scope module srl16e $end
+$var wire 1 ` A0 $end
+$var wire 1 a A1 $end
+$var wire 1 b A2 $end
+$var wire 1 c A3 $end
+$var wire 1 E CE $end
+$var wire 1 ? CLK $end
+$var wire 1 d D $end
+$var wire 1 e Q $end
+$var reg 16 f data [15:0] $end
+$upscope $end
+$upscope $end
+$scope begin gen_srl16[4] $end
+$scope module srl16e $end
+$var wire 1 g A0 $end
+$var wire 1 h A1 $end
+$var wire 1 i A2 $end
+$var wire 1 j A3 $end
+$var wire 1 E CE $end
+$var wire 1 ? CLK $end
+$var wire 1 k D $end
+$var wire 1 l Q $end
+$var reg 16 m data [15:0] $end
+$upscope $end
+$upscope $end
+$scope begin gen_srl16[5] $end
+$scope module srl16e $end
+$var wire 1 n A0 $end
+$var wire 1 o A1 $end
+$var wire 1 p A2 $end
+$var wire 1 q A3 $end
+$var wire 1 E CE $end
+$var wire 1 ? CLK $end
+$var wire 1 r D $end
+$var wire 1 s Q $end
+$var reg 16 t data [15:0] $end
+$upscope $end
+$upscope $end
+$scope begin gen_srl16[6] $end
+$scope module srl16e $end
+$var wire 1 u A0 $end
+$var wire 1 v A1 $end
+$var wire 1 w A2 $end
+$var wire 1 x A3 $end
+$var wire 1 E CE $end
+$var wire 1 ? CLK $end
+$var wire 1 y D $end
+$var wire 1 z Q $end
+$var reg 16 { data [15:0] $end
+$upscope $end
+$upscope $end
+$scope begin gen_srl16[7] $end
+$scope module srl16e $end
+$var wire 1 | A0 $end
+$var wire 1 } A1 $end
+$var wire 1 ~ A2 $end
+$var wire 1 !" A3 $end
+$var wire 1 E CE $end
+$var wire 1 ? CLK $end
+$var wire 1 "" D $end
+$var wire 1 #" Q $end
+$var reg 16 $" data [15:0] $end
+$upscope $end
+$upscope $end
+$scope begin gen_srl16[8] $end
+$scope module srl16e $end
+$var wire 1 %" A0 $end
+$var wire 1 &" A1 $end
+$var wire 1 '" A2 $end
+$var wire 1 (" A3 $end
+$var wire 1 E CE $end
+$var wire 1 ? CLK $end
+$var wire 1 )" D $end
+$var wire 1 *" Q $end
+$var reg 16 +" data [15:0] $end
+$upscope $end
+$upscope $end
+$scope begin gen_srl16[9] $end
+$scope module srl16e $end
+$var wire 1 ," A0 $end
+$var wire 1 -" A1 $end
+$var wire 1 ." A2 $end
+$var wire 1 /" A3 $end
+$var wire 1 E CE $end
+$var wire 1 ? CLK $end
+$var wire 1 0" D $end
+$var wire 1 1" Q $end
+$var reg 16 2" data [15:0] $end
+$upscope $end
+$upscope $end
+$scope begin gen_srl16[10] $end
+$scope module srl16e $end
+$var wire 1 3" A0 $end
+$var wire 1 4" A1 $end
+$var wire 1 5" A2 $end
+$var wire 1 6" A3 $end
+$var wire 1 E CE $end
+$var wire 1 ? CLK $end
+$var wire 1 7" D $end
+$var wire 1 8" Q $end
+$var reg 16 9" data [15:0] $end
+$upscope $end
+$upscope $end
+$scope begin gen_srl16[11] $end
+$scope module srl16e $end
+$var wire 1 :" A0 $end
+$var wire 1 ;" A1 $end
+$var wire 1 <" A2 $end
+$var wire 1 =" A3 $end
+$var wire 1 E CE $end
+$var wire 1 ? CLK $end
+$var wire 1 >" D $end
+$var wire 1 ?" Q $end
+$var reg 16 @" data [15:0] $end
+$upscope $end
+$upscope $end
+$scope begin gen_srl16[12] $end
+$scope module srl16e $end
+$var wire 1 A" A0 $end
+$var wire 1 B" A1 $end
+$var wire 1 C" A2 $end
+$var wire 1 D" A3 $end
+$var wire 1 E CE $end
+$var wire 1 ? CLK $end
+$var wire 1 E" D $end
+$var wire 1 F" Q $end
+$var reg 16 G" data [15:0] $end
+$upscope $end
+$upscope $end
+$scope begin gen_srl16[13] $end
+$scope module srl16e $end
+$var wire 1 H" A0 $end
+$var wire 1 I" A1 $end
+$var wire 1 J" A2 $end
+$var wire 1 K" A3 $end
+$var wire 1 E CE $end
+$var wire 1 ? CLK $end
+$var wire 1 L" D $end
+$var wire 1 M" Q $end
+$var reg 16 N" data [15:0] $end
+$upscope $end
+$upscope $end
+$scope begin gen_srl16[14] $end
+$scope module srl16e $end
+$var wire 1 O" A0 $end
+$var wire 1 P" A1 $end
+$var wire 1 Q" A2 $end
+$var wire 1 R" A3 $end
+$var wire 1 E CE $end
+$var wire 1 ? CLK $end
+$var wire 1 S" D $end
+$var wire 1 T" Q $end
+$var reg 16 U" data [15:0] $end
+$upscope $end
+$upscope $end
+$scope begin gen_srl16[15] $end
+$scope module srl16e $end
+$var wire 1 V" A0 $end
+$var wire 1 W" A1 $end
+$var wire 1 X" A2 $end
+$var wire 1 Y" A3 $end
+$var wire 1 E CE $end
+$var wire 1 ? CLK $end
+$var wire 1 Z" D $end
+$var wire 1 [" Q $end
+$var reg 16 \" data [15:0] $end
+$upscope $end
+$upscope $end
+$scope begin gen_srl16[16] $end
+$scope module srl16e $end
+$var wire 1 ]" A0 $end
+$var wire 1 ^" A1 $end
+$var wire 1 _" A2 $end
+$var wire 1 `" A3 $end
+$var wire 1 E CE $end
+$var wire 1 ? CLK $end
+$var wire 1 a" D $end
+$var wire 1 b" Q $end
+$var reg 16 c" data [15:0] $end
+$upscope $end
+$upscope $end
+$scope begin gen_srl16[17] $end
+$scope module srl16e $end
+$var wire 1 d" A0 $end
+$var wire 1 e" A1 $end
+$var wire 1 f" A2 $end
+$var wire 1 g" A3 $end
+$var wire 1 E CE $end
+$var wire 1 ? CLK $end
+$var wire 1 h" D $end
+$var wire 1 i" Q $end
+$var reg 16 j" data [15:0] $end
+$upscope $end
+$upscope $end
+$scope begin gen_srl16[18] $end
+$scope module srl16e $end
+$var wire 1 k" A0 $end
+$var wire 1 l" A1 $end
+$var wire 1 m" A2 $end
+$var wire 1 n" A3 $end
+$var wire 1 E CE $end
+$var wire 1 ? CLK $end
+$var wire 1 o" D $end
+$var wire 1 p" Q $end
+$var reg 16 q" data [15:0] $end
+$upscope $end
+$upscope $end
+$scope begin gen_srl16[19] $end
+$scope module srl16e $end
+$var wire 1 r" A0 $end
+$var wire 1 s" A1 $end
+$var wire 1 t" A2 $end
+$var wire 1 u" A3 $end
+$var wire 1 E CE $end
+$var wire 1 ? CLK $end
+$var wire 1 v" D $end
+$var wire 1 w" Q $end
+$var reg 16 x" data [15:0] $end
+$upscope $end
+$upscope $end
+$scope begin gen_srl16[20] $end
+$scope module srl16e $end
+$var wire 1 y" A0 $end
+$var wire 1 z" A1 $end
+$var wire 1 {" A2 $end
+$var wire 1 |" A3 $end
+$var wire 1 E CE $end
+$var wire 1 ? CLK $end
+$var wire 1 }" D $end
+$var wire 1 ~" Q $end
+$var reg 16 !# data [15:0] $end
+$upscope $end
+$upscope $end
+$scope begin gen_srl16[21] $end
+$scope module srl16e $end
+$var wire 1 "# A0 $end
+$var wire 1 ## A1 $end
+$var wire 1 $# A2 $end
+$var wire 1 %# A3 $end
+$var wire 1 E CE $end
+$var wire 1 ? CLK $end
+$var wire 1 &# D $end
+$var wire 1 '# Q $end
+$var reg 16 (# data [15:0] $end
+$upscope $end
+$upscope $end
+$scope begin gen_srl16[22] $end
+$scope module srl16e $end
+$var wire 1 )# A0 $end
+$var wire 1 *# A1 $end
+$var wire 1 +# A2 $end
+$var wire 1 ,# A3 $end
+$var wire 1 E CE $end
+$var wire 1 ? CLK $end
+$var wire 1 -# D $end
+$var wire 1 .# Q $end
+$var reg 16 /# data [15:0] $end
+$upscope $end
+$upscope $end
+$scope begin gen_srl16[23] $end
+$scope module srl16e $end
+$var wire 1 0# A0 $end
+$var wire 1 1# A1 $end
+$var wire 1 2# A2 $end
+$var wire 1 3# A3 $end
+$var wire 1 E CE $end
+$var wire 1 ? CLK $end
+$var wire 1 4# D $end
+$var wire 1 5# Q $end
+$var reg 16 6# data [15:0] $end
+$upscope $end
+$upscope $end
+$scope begin gen_srl16[24] $end
+$scope module srl16e $end
+$var wire 1 7# A0 $end
+$var wire 1 8# A1 $end
+$var wire 1 9# A2 $end
+$var wire 1 :# A3 $end
+$var wire 1 E CE $end
+$var wire 1 ? CLK $end
+$var wire 1 ;# D $end
+$var wire 1 <# Q $end
+$var reg 16 =# data [15:0] $end
+$upscope $end
+$upscope $end
+$scope begin gen_srl16[25] $end
+$scope module srl16e $end
+$var wire 1 ># A0 $end
+$var wire 1 ?# A1 $end
+$var wire 1 @# A2 $end
+$var wire 1 A# A3 $end
+$var wire 1 E CE $end
+$var wire 1 ? CLK $end
+$var wire 1 B# D $end
+$var wire 1 C# Q $end
+$var reg 16 D# data [15:0] $end
+$upscope $end
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diff --git a/control_lib/newfifo/fifo_short.v b/control_lib/newfifo/fifo_short.v
new file mode 100644
index 000000000..53a7603c7
--- /dev/null
+++ b/control_lib/newfifo/fifo_short.v
@@ -0,0 +1,95 @@
+
+module fifo_short
+  #(parameter WIDTH=32)
+   (input clk, input reset, input clear,
+    input [WIDTH-1:0] datain,
+    input src_rdy_i,
+    output dst_rdy_o,
+    output [WIDTH-1:0] dataout,
+    output src_rdy_o,
+    input dst_rdy_i,
+    
+    output reg [4:0] space,
+    output reg [4:0] occupied);
+
+   reg full, empty;
+   wire write 	     = src_rdy_i & dst_rdy_o;
+   wire read 	     = dst_rdy_i & src_rdy_o;
+
+   assign dst_rdy_o  = ~full;
+   assign src_rdy_o  = ~empty;
+   
+   reg [3:0] 	  a;
+   genvar 	  i;
+   
+   generate
+      for (i=0;i<WIDTH;i=i+1)
+	begin : gen_srl16
+	   SRL16E
+	     srl16e(.Q(dataout[i]),
+		    .A0(a[0]),.A1(a[1]),.A2(a[2]),.A3(a[3]),
+		    .CE(write),.CLK(clk),.D(datain[i]));
+	end
+   endgenerate
+   
+   always @(posedge clk)
+     if(reset)
+       begin
+	  a <= 0;
+	  empty <= 1;
+	  full <= 0;
+       end
+     else if(clear)
+       begin
+	  a <= 0;
+	  empty <= 1;
+	  full<= 0;
+       end
+     else if(read & ~write)
+       begin
+	  full <= 0;
+	  if(a==0)
+	    empty <= 1;
+	  else
+	    a <= a - 1;
+       end
+     else if(write & ~read)
+       begin
+	  empty <= 0;
+	  if(~empty)
+	    a <= a + 1;
+	  if(a == 14)
+	    full <= 1;
+       end
+
+   // NOTE will fail if you write into a full fifo or read from an empty one
+
+   //////////////////////////////////////////////////////////////
+   // space and occupied are used for diagnostics, not 
+   // guaranteed correct
+   
+   //assign space = full ? 0 : empty ? 16 : 15-a;
+   //assign occupied = empty ? 0 : full ? 16 : a+1;
+
+   always @(posedge clk)
+     if(reset)
+       space <= 16;
+     else if(clear)
+       space <= 16;
+     else if(read & ~write)
+       space <= space + 1;
+     else if(write & ~read)
+       space <= space - 1;
+   
+   always @(posedge clk)
+     if(reset)
+       occupied <= 0;
+     else if(clear)
+       occupied <= 0;
+     else if(read & ~write)
+       occupied <= occupied - 1;
+     else if(write & ~read)
+       occupied <= occupied + 1;
+      
+endmodule // fifo_short
+
diff --git a/control_lib/newfifo/fifo_spec.txt b/control_lib/newfifo/fifo_spec.txt
new file mode 100644
index 000000000..133b9fa8e
--- /dev/null
+++ b/control_lib/newfifo/fifo_spec.txt
@@ -0,0 +1,36 @@
+
+
+FIFO and Buffer Interface Spec
+
+Buffer Interface Data Wires -- matches fifo36
+     DATA[31:0]
+     FLAGS[3:0]
+     Bit 0	SOP
+     Bit 1	EOP
+	If SOP=1 && EOP=1, OCC contains error flags
+     Bits 3:2	OCC[1:0] --> 00 = all 4 bytes
+		     01 = 1 byte
+		     10 = 2 bytes
+		     11 = 3 bytes
+
+fifo36 -->  {OCC[1:0],EOP,SOP,DATA[31:0]}
+       OCC same as buffer interface
+
+fifo19 -->  {OCC,EOP,SOP,DATA[15:0]}    
+       Doesn't fit well into BRAM, dist RAM ok
+       OCC = 1 means last word is half full
+	   = 0 means last word is full
+
+fifo18 -->  {EOP,SOP,DATA[15:0]}
+       No half-word capability?  Should we drop sop instead?
+
+Control Wires - Data into FIFO
+	SRC_RDY_i    Upstream has data for me
+	DST_RDY_o    I have space
+		     Transfer occurs if SRC_RDI_i && DST_RDY_o
+	
+Control Wires - Data out of FIFO
+	SRC_RDY_o    I have data for downstream
+	DST_RDY_i    Downstream has space
+		     Transfer occurs if SRC_RDI_o && DST_RDY_i
+	
diff --git a/control_lib/newfifo/fifo_tb.v b/control_lib/newfifo/fifo_tb.v
new file mode 100644
index 000000000..98fd63f8d
--- /dev/null
+++ b/control_lib/newfifo/fifo_tb.v
@@ -0,0 +1,155 @@
+module fifo_tb();
+   
+   reg clk, rst;
+   wire short_full, short_empty, long_full, long_empty;
+   wire casc_full, casc_empty, casc2_full, casc2_empty;
+   reg 	read, write;
+   
+   wire [7:0] short_do, long_do;
+   wire [7:0] casc_do, casc2_do;
+   reg [7:0]  di;
+
+   reg 	      clear = 0;
+   
+   shortfifo #(.WIDTH(8)) shortfifo
+     (.clk(clk),.rst(rst),.datain(di),.dataout(short_do),.clear(clear),
+      .read(read),.write(write),.full(short_full),.empty(short_empty));
+   
+   longfifo #(.WIDTH(8), .SIZE(4)) longfifo
+     (.clk(clk),.rst(rst),.datain(di),.dataout(long_do),.clear(clear),
+      .read(read),.write(write),.full(long_full),.empty(long_empty));
+   
+   cascadefifo #(.WIDTH(8), .SIZE(4)) cascadefifo
+     (.clk(clk),.rst(rst),.datain(di),.dataout(casc_do),.clear(clear),
+      .read(read),.write(write),.full(casc_full),.empty(casc_empty));
+   
+   cascadefifo2 #(.WIDTH(8), .SIZE(4)) cascadefifo2
+     (.clk(clk),.rst(rst),.datain(di),.dataout(casc2_do),.clear(clear),
+      .read(read),.write(write),.full(casc2_full),.empty(casc2_empty));
+   
+   initial rst = 1;
+   initial #1000 rst = 0;
+   initial clk = 0;
+   always #50 clk = ~clk;
+   
+   initial di = 8'hAE;
+   initial read = 0;
+   initial write = 0;
+
+   always @(posedge clk)
+     if(write)
+       di <= di + 1;
+   
+   always @(posedge clk)
+     begin
+	if(short_full != long_full)
+	  $display("Error: FULL mismatch");
+	if(short_empty != long_empty)
+	  $display("Note: EMPTY mismatch, usually not a problem (longfifo has 2 cycle latency)");
+	if(read & (short_do != long_do))
+	  $display("Error: DATA mismatch");
+     end
+   
+   initial $dumpfile("fifo_tb.vcd");
+   initial $dumpvars(0,fifo_tb);
+
+   initial
+     begin
+	@(negedge rst);
+	@(posedge clk);
+	repeat (10)
+	  @(posedge clk);
+	write <= 1;
+	@(posedge clk);
+	write <= 0;
+	@(posedge clk);
+	@(posedge clk);
+	@(posedge clk);
+	@(posedge clk);
+	@(posedge clk);
+	@(posedge clk);
+	@(posedge clk);
+	@(posedge clk);
+	read <= 1;
+	@(posedge clk);
+	read <= 0;
+	@(posedge clk);
+	@(posedge clk);
+	@(posedge clk);
+	@(posedge clk);
+	@(posedge clk);
+
+	repeat(10)
+	  begin
+	     write <= 1;
+	     @(posedge clk);
+	     write <= 0;
+	     @(posedge clk);
+	     @(posedge clk);
+	     @(posedge clk);
+	     read <= 1;
+	     @(posedge clk);
+	     read <= 0;
+	     @(posedge clk);
+	     @(posedge clk);
+	     @(posedge clk);
+	     @(posedge clk);
+	     @(posedge clk);
+	  end // repeat (10)
+	
+	write <= 1;
+	repeat (4)
+	  @(posedge clk);
+	write <= 0;
+	@(posedge clk);
+	read <= 1;
+	repeat (4)
+	  @(posedge clk);
+	read <= 0;
+	@(posedge clk);
+
+
+	write <= 1;
+	repeat (4)
+	  @(posedge clk);
+	write <= 0;
+	@(posedge clk);
+	repeat (4)
+	  begin
+	     read <= 1;
+	     @(posedge clk);
+	     read <= 0;
+	     @(posedge clk);
+	  end
+
+	write <= 1;
+	@(posedge clk);
+	@(posedge clk);
+	@(posedge clk);
+	@(posedge clk);
+	read <= 1;
+	repeat (5)
+	  @(posedge clk);
+	write <= 0;
+	  @(posedge clk);
+	  @(posedge clk);
+	read <= 0;
+	@(posedge clk);
+
+	write <= 1;
+	repeat (16)
+	  @(posedge clk);
+	write <= 0;
+	@(posedge clk);
+	
+	read <= 1;
+	repeat (16)
+	  @(posedge clk);
+	read <= 0;
+	@(posedge clk);
+		 
+	repeat (10)
+	  @(posedge clk);
+	$finish;
+     end
+endmodule // longfifo_tb
diff --git a/control_lib/newfifo/ll8_to_fifo19.v b/control_lib/newfifo/ll8_to_fifo19.v
new file mode 100644
index 000000000..c65be5136
--- /dev/null
+++ b/control_lib/newfifo/ll8_to_fifo19.v
@@ -0,0 +1,77 @@
+
+module ll8_to_fifo19
+  (input clk, input reset, input clear,
+   input [7:0] ll_data,
+   input ll_sof_n,
+   input ll_eof_n,
+   input ll_src_rdy_n,
+   output ll_dst_rdy_n,
+
+   output [18:0] f19_data,
+   output f19_src_rdy_o,
+   input f19_dst_rdy_i );
+
+   // Why anybody would use active low in an FPGA is beyond me...
+   wire  ll_sof      = ~ll_sof_n;
+   wire  ll_eof      = ~ll_eof_n;
+   wire  ll_src_rdy  = ~ll_src_rdy_n;
+   wire  ll_dst_rdy;
+   assign    ll_dst_rdy_n  = ~ll_dst_rdy;
+
+   wire xfer_out 	   = f19_src_rdy_o & f19_dst_rdy_i;
+   //  wire xfer_in 	   = ll_src_rdy & ll_dst_rdy;   Not needed
+   
+   reg 	 f19_sof, f19_eof, f19_occ;
+   
+   reg [1:0] state;
+   reg [7:0] dat0, dat1;
+
+   always @(posedge clk)
+     if(ll_src_rdy & ((state==0)|xfer_out))
+       f19_sof <= ll_sof;
+
+   always @(posedge clk)
+     if(ll_src_rdy & ((state != 2)|xfer_out))
+       f19_eof <= ll_eof;
+
+   always @(posedge clk)
+     if(ll_eof)
+       f19_occ <= ~state[0];
+     else
+       f19_occ <= 0;
+   
+   always @(posedge clk)
+     if(reset)
+       state   <= 0;
+     else
+       if(ll_src_rdy)
+	 case(state)
+	   0 : 
+	     if(ll_eof)
+	       state <= 2;
+	     else
+	       state <= 1;
+	   1 : 
+	     state <= 2;
+	   2 : 
+	     if(xfer_out)
+	       state 	   <= 1;
+	 endcase // case(state)
+       else
+	 if(xfer_out)
+	   state 	   <= 0;
+
+   always @(posedge clk)
+     if(ll_src_rdy & (state==1))
+       dat1 		   <= ll_data;
+
+   always @(posedge clk)
+     if(ll_src_rdy & ((state==0) | xfer_out))
+       dat0 		   <= ll_data;
+   
+   assign    ll_dst_rdy     = xfer_out | (state != 2);
+   assign    f19_data 	    = {f19_occ,f19_eof,f19_sof,dat0,dat1};
+   assign    f19_src_rdy_o  = (state == 2);
+      
+endmodule // ll8_to_fifo19
+
diff --git a/control_lib/newfifo/ll8_to_fifo36.v b/control_lib/newfifo/ll8_to_fifo36.v
new file mode 100644
index 000000000..0d772c45c
--- /dev/null
+++ b/control_lib/newfifo/ll8_to_fifo36.v
@@ -0,0 +1,94 @@
+
+module ll8_to_fifo36
+  (input clk, reset,
+   input [7:0] ll_data,
+   input ll_sof_n,
+   input ll_eof_n,
+   input ll_src_rdy_n,
+   output ll_dst_rdy_n,
+
+   output [35:0] f36_data,
+   output f36_src_rdy_o,
+   input f36_dst_rdy_i );
+
+   wire f36_full     = ~f36_dst_rdy_i;
+   wire f36_write    = f36_src_rdy_o & f36_dst_rdy_i;
+      
+   // Why anybody would use active low in an FPGA is beyond me...
+   wire  ll_sof      = ~ll_sof_n;
+   wire  ll_eof      = ~ll_eof_n;
+   wire  ll_src_rdy  = ~ll_src_rdy_n;
+   wire  ll_dst_rdy;
+   assign    ll_dst_rdy_n = ~ll_dst_rdy;
+
+   reg 	 f36_sof, f36_eof;
+   reg [1:0] f36_occ;
+   
+   
+   reg [2:0] state;
+   reg [7:0] dat0, dat1, dat2, dat3;
+
+   always @(posedge clk)
+     if(ll_src_rdy & ((state==0)|f36_write))
+       f36_sof <= ll_sof;
+
+   always @(posedge clk)
+     if(ll_src_rdy & ((state !=4)|f36_write))
+       f36_eof <= ll_eof;
+
+   always @(posedge clk)
+     if(ll_eof)
+       f36_occ <= state[1:0];
+     else
+       f36_occ <= 0;
+   
+   always @(posedge clk)
+     if(reset)
+       state   <= 0;
+     else
+       if(ll_src_rdy)
+	 case(state)
+	   0 : 
+	     if(ll_eof)
+	       state <= 4;
+	     else
+	       state <= 1;
+	   1 : 
+	     if(ll_eof)
+	       state <= 4;
+	     else
+	       state <= 2;
+	   2 : 
+	     if(ll_eof)
+	       state <= 4;
+	     else 
+	       state <= 3;
+	   3 : state <= 4;
+	   4 : if(~f36_full)
+	     state 	   <= 1;
+	 endcase // case(state)
+       else
+	 if(f36_write)
+	   state 	   <= 0;
+
+   always @(posedge clk)
+     if(ll_src_rdy & (state==3))
+       dat3 		   <= ll_data;
+
+   always @(posedge clk)
+     if(ll_src_rdy & (state==2))
+       dat2 		   <= ll_data;
+
+   always @(posedge clk)
+     if(ll_src_rdy & (state==1))
+       dat1 		   <= ll_data;
+
+   always @(posedge clk)
+     if(ll_src_rdy & ((state==0) | f36_write))
+       dat0 		   <= ll_data;
+   
+   assign    ll_dst_rdy     = ~f36_full | (state != 4);
+   assign    f36_data 	    = {f36_occ,f36_eof,f36_sof,dat0,dat1,dat2,dat3};  // FIXME endianess
+   assign    f36_src_rdy_o  = (state == 4);
+      
+endmodule // ll8_to_fifo36