diff options
author | Matt Ettus <matt@ettus.com> | 2009-09-02 17:56:26 -0700 |
---|---|---|
committer | Matt Ettus <matt@ettus.com> | 2009-09-02 17:56:26 -0700 |
commit | 09951ed9ba4758cc7cced26c1f673545284c5cf3 (patch) | |
tree | 7df471b1692ae1fe5e8c2b78f1506f27d129d7b8 /control_lib/newfifo/fifo_2clock_cascade.v | |
parent | fb04ad0eb86ea0cfa65be66c09c8424213c9c932 (diff) | |
download | uhd-09951ed9ba4758cc7cced26c1f673545284c5cf3.tar.gz uhd-09951ed9ba4758cc7cced26c1f673545284c5cf3.tar.bz2 uhd-09951ed9ba4758cc7cced26c1f673545284c5cf3.zip |
major cleanup of 2 clock fifos
Diffstat (limited to 'control_lib/newfifo/fifo_2clock_cascade.v')
-rw-r--r-- | control_lib/newfifo/fifo_2clock_cascade.v | 44 |
1 files changed, 26 insertions, 18 deletions
diff --git a/control_lib/newfifo/fifo_2clock_cascade.v b/control_lib/newfifo/fifo_2clock_cascade.v index 2abbbf3b5..8d8a47954 100644 --- a/control_lib/newfifo/fifo_2clock_cascade.v +++ b/control_lib/newfifo/fifo_2clock_cascade.v @@ -1,27 +1,35 @@ -module cascadefifo_2clock - #(parameter DWIDTH=32, AWIDTH=9) - (input wclk, input [DWIDTH-1:0] datain, input src_rdy_i, output dst_rdy_o, output [AWIDTH-1:0] level_wclk, - input rclk, output [DWIDTH-1:0] dataout, output src_rdy_o, input dst_rdy_i, output [AWIDTH-1:0] level_rclk, - input arst); - - wire [DWIDTH-1:0] data_int1, data_int2; - wire src_rdy_int1, src_rdy_int2, dst_rdy_int1, dst_rdy_int2; +module fifo_2clock_cascade + #(parameter WIDTH=32, SIZE=9) + (input wclk, input [WIDTH-1:0] datain, input src_rdy_i, output dst_rdy_o, output [15:0] space, + input rclk, output [WIDTH-1:0] dataout, output src_rdy_o, input dst_rdy_i, output [15:0] occupied, + input arst); + + wire [WIDTH-1:0] data_int1, data_int2; + wire src_rdy_int1, src_rdy_int2, dst_rdy_int1, dst_rdy_int2; + wire [SIZE-1:0] level_wclk, level_rclk; + wire [4:0] s1_space, s1_occupied, s2_space, s2_occupied; + wire [15:0] l_space, l_occupied; - fifo_short #(.WIDTH(DWIDTH)) shortfifo + fifo_short #(.WIDTH(WIDTH)) shortfifo (.clk(wclk), .reset(arst), .clear(0), .datain(datain), .src_rdy_i(src_rdy_i), .dst_rdy_o(dst_rdy_o), - .dataout(data_int1), .src_rdy_o(src_rdy_int1), .dst_rdy_i(dst_rdy_int1) ); + .dataout(data_int1), .src_rdy_o(src_rdy_int1), .dst_rdy_i(dst_rdy_int1), + .space(s1_space), .occupied(s1_occupied) ); - newfifo_2clock #(.DWIDTH(DWIDTH),.AWIDTH(AWIDTH)) fifo_2clock - (.wclk(wclk), .datain(data_int1), .src_rdy_i(src_rdy_int1), .dst_rdy_o(dst_rdy_int1), .level_wclk(level_wclk), - .rclk(rclk), .dataout(data_int2), .src_rdy_o(src_rdy_int2), .dst_rdy_i(dst_rdy_int2), .level_rclk(level_rclk), + fifo_2clock #(.DWIDTH(WIDTH),.SIZE(SIZE)) fifo_2clock + (.wclk(wclk), .datain(data_int1), .src_rdy_i(src_rdy_int1), .dst_rdy_o(dst_rdy_int1), .space(l_space), + .rclk(rclk), .dataout(data_int2), .src_rdy_o(src_rdy_int2), .dst_rdy_i(dst_rdy_int2), .occupied(l_occupied), .arst(arst) ); - - fifo_short #(.WIDTH(DWIDTH)) shortfifo2 + + fifo_short #(.WIDTH(WIDTH)) shortfifo2 (.clk(rclk), .reset(arst), .clear(0), .datain(data_int2), .src_rdy_i(src_rdy_int2), .dst_rdy_o(dst_rdy_int2), - .dataout(dataout), .src_rdy_o(src_rdy_o), .dst_rdy_i(dst_rdy_i) ); - -endmodule // fifo_2clock_casc + .dataout(dataout), .src_rdy_o(src_rdy_o), .dst_rdy_i(dst_rdy_i), + .space(s2_space), .occupied(s2_occupied)); + // Be conservative -- Only advertise space from input side of fifo, occupied from output side + assign space = {11'b0,s1_space} + l_space; + assign occupied = {11'b0,s2_occupied} + l_occupied; + +endmodule // fifo_2clock_cascade |