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author | Matt Ettus <matt@ettus.com> | 2009-09-10 21:52:06 -0700 |
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committer | Matt Ettus <matt@ettus.com> | 2009-09-10 21:52:06 -0700 |
commit | 2f3e0eefe01b61f8e5e12d2ceef6990abb8a1ff3 (patch) | |
tree | 38845a43e869454ed88fc68d26c56b7aa3b49e97 /control_lib/newfifo/fifo_2clock.v | |
parent | 38e0c588af094e7f809ad73981a3ba002d2c936d (diff) | |
download | uhd-2f3e0eefe01b61f8e5e12d2ceef6990abb8a1ff3.tar.gz uhd-2f3e0eefe01b61f8e5e12d2ceef6990abb8a1ff3.tar.bz2 uhd-2f3e0eefe01b61f8e5e12d2ceef6990abb8a1ff3.zip |
More xilinx fifos, more clean up of our fifos
Diffstat (limited to 'control_lib/newfifo/fifo_2clock.v')
-rw-r--r-- | control_lib/newfifo/fifo_2clock.v | 42 |
1 files changed, 27 insertions, 15 deletions
diff --git a/control_lib/newfifo/fifo_2clock.v b/control_lib/newfifo/fifo_2clock.v index 2ada39fb0..07ae090f2 100644 --- a/control_lib/newfifo/fifo_2clock.v +++ b/control_lib/newfifo/fifo_2clock.v @@ -16,21 +16,33 @@ module fifo_2clock assign read = src_rdy_o & dst_rdy_i; generate - if(SIZE==9) - fifo_xlnx_512x36_2clk mac_tx_fifo_2clk - (.rst(rst), - .wr_clk(wclk),.din(datain),.full(full),.wr_en(write),.wr_data_count(level_wclk), - .rd_clk(rclk),.dout(dataout),.empty(empty),.rd_en(read),.rd_data_count(level_rclk) ); - else if(SIZE==11) - fifo_xlnx_2Kx36_2clk mac_tx_fifo_2clk - (.rst(rst), - .wr_clk(wclk),.din(datain),.full(full),.wr_en(write),.wr_data_count(level_wclk), - .rd_clk(rclk),.dout(dataout),.empty(empty),.rd_en(read),.rd_data_count(level_rclk) ); - else if(SIZE==6) - fifo_xlnx_64x36_2clk mac_tx_fifo_2clk - (.rst(rst), - .wr_clk(wclk),.din(datain),.full(full),.wr_en(write),.wr_data_count(level_wclk), - .rd_clk(rclk),.dout(dataout),.empty(empty),.rd_en(read),.rd_data_count(level_rclk) ); + if(WIDTH==36) + if(SIZE==9) + fifo_xlnx_512x36_2clk fifo_xlnx_512x36_2clk + (.rst(rst), + .wr_clk(wclk),.din(datain),.full(full),.wr_en(write),.wr_data_count(level_wclk), + .rd_clk(rclk),.dout(dataout),.empty(empty),.rd_en(read),.rd_data_count(level_rclk) ); + else if(SIZE==11) + fifo_xlnx_2Kx36_2clk fifo_xlnx_2Kx36_2clk + (.rst(rst), + .wr_clk(wclk),.din(datain),.full(full),.wr_en(write),.wr_data_count(level_wclk), + .rd_clk(rclk),.dout(dataout),.empty(empty),.rd_en(read),.rd_data_count(level_rclk) ); + else if(SIZE==6) + fifo_xlnx_64x36_2clk fifo_xlnx_64x36_2clk + (.rst(rst), + .wr_clk(wclk),.din(datain),.full(full),.wr_en(write),.wr_data_count(level_wclk), + .rd_clk(rclk),.dout(dataout),.empty(empty),.rd_en(read),.rd_data_count(level_rclk) ); + else + fifo_xlnx_512x36_2clk fifo_xlnx_512x36_2clk + (.rst(rst), + .wr_clk(wclk),.din(datain),.full(full),.wr_en(write),.wr_data_count(level_wclk), + .rd_clk(rclk),.dout(dataout),.empty(empty),.rd_en(read),.rd_data_count(level_rclk) ); + else if((WIDTH==19)|(WIDTH==18)) + if(SIZE==4) + fifo_xlnx_16x19_2clk fifo_xlnx_16x19_2clk + (.rst(rst), + .wr_clk(wclk),.din(datain),.full(full),.wr_en(write),.wr_data_count(level_wclk), + .rd_clk(rclk),.dout(dataout),.empty(empty),.rd_en(read),.rd_data_count(level_rclk) ); endgenerate assign occupied = {{(16-SIZE-1){1'b0}},level_rclk}; |