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author | matt <matt@221aa14e-8319-0410-a670-987f0aec2ac5> | 2009-03-30 02:54:51 +0000 |
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committer | matt <matt@221aa14e-8319-0410-a670-987f0aec2ac5> | 2009-03-30 02:54:51 +0000 |
commit | a4b5b6839293b624e66a5fbcbc6bb822cadfb3b5 (patch) | |
tree | d18e7db5445e9f029711e3eb8468be666efdf12e /control_lib/newfifo/fifo36_to_fifo19.v | |
parent | 9e643a57af8f84f6008607d0554896d0206c7cf5 (diff) | |
download | uhd-a4b5b6839293b624e66a5fbcbc6bb822cadfb3b5.tar.gz uhd-a4b5b6839293b624e66a5fbcbc6bb822cadfb3b5.tar.bz2 uhd-a4b5b6839293b624e66a5fbcbc6bb822cadfb3b5.zip |
new fifos copied over from other project
git-svn-id: http://gnuradio.org/svn/gnuradio/trunk@10709 221aa14e-8319-0410-a670-987f0aec2ac5
Diffstat (limited to 'control_lib/newfifo/fifo36_to_fifo19.v')
-rw-r--r-- | control_lib/newfifo/fifo36_to_fifo19.v | 41 |
1 files changed, 41 insertions, 0 deletions
diff --git a/control_lib/newfifo/fifo36_to_fifo19.v b/control_lib/newfifo/fifo36_to_fifo19.v new file mode 100644 index 000000000..de249aaeb --- /dev/null +++ b/control_lib/newfifo/fifo36_to_fifo19.v @@ -0,0 +1,41 @@ + +module fifo36_to_fifo19 + (input clk, input reset, input clear, + input [35:0] f36_datain, + input f36_src_rdy_i, + output f36_dst_rdy_o, + + output [18:0] f19_dataout, + output f19_src_rdy_o, + input f19_dst_rdy_i ); + + wire f36_sof = f36_datain[32]; + wire f36_eof = f36_datain[33]; + wire f36_occ = f36_datain[35:34]; + + reg phase; + + wire half_line = f36_eof & ((f36_occ==1)|(f36_occ==2)); + + assign f19_dataout[15:0] = phase ? f36_datain[15:0] : f36_datain[31:16]; + assign f19_dataout[16] = phase ? 0 : f36_sof; + assign f19_dataout[17] = phase ? f36_eof : half_line; + assign f19_dataout[18] = f19_dataout[17] & ((f36_occ==1)|(f36_occ==3)); + + assign f19_src_rdy_o = f36_src_rdy_i; + assign f36_dst_rdy_o = (phase | half_line) & f19_dst_rdy_i; + + wire f19_xfer = f19_src_rdy_o & f19_dst_rdy_i; + wire f36_xfer = f36_src_rdy_i & f36_dst_rdy_o; + + always @(posedge clk) + if(reset) + phase <= 0; + else if(f36_xfer) + phase <= 0; + else if(f19_xfer) + phase <= 1; + + +endmodule // fifo36_to_fifo19 + |