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author | Matt Ettus <matt@ettus.com> | 2009-09-02 17:23:12 -0700 |
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committer | Matt Ettus <matt@ettus.com> | 2009-09-02 17:23:12 -0700 |
commit | a3ebf209706e424df88a0f5abbb12b80147c922b (patch) | |
tree | b99056235d25606352a5f05d22b1099d202dd664 /control_lib/fifo_tb.v | |
parent | 280e196b60f0a4e8f1915dbd38761e879ccd567e (diff) | |
download | uhd-a3ebf209706e424df88a0f5abbb12b80147c922b.tar.gz uhd-a3ebf209706e424df88a0f5abbb12b80147c922b.tar.bz2 uhd-a3ebf209706e424df88a0f5abbb12b80147c922b.zip |
cascadefifo.v wasn't used, only the double cascade version. fifo_2clock.v and fifo_2clock.v are empty
Diffstat (limited to 'control_lib/fifo_tb.v')
-rw-r--r-- | control_lib/fifo_tb.v | 8 |
1 files changed, 2 insertions, 6 deletions
diff --git a/control_lib/fifo_tb.v b/control_lib/fifo_tb.v index 98fd63f8d..616fe4ee7 100644 --- a/control_lib/fifo_tb.v +++ b/control_lib/fifo_tb.v @@ -2,11 +2,11 @@ module fifo_tb(); reg clk, rst; wire short_full, short_empty, long_full, long_empty; - wire casc_full, casc_empty, casc2_full, casc2_empty; + wire casc2_full, casc2_empty; reg read, write; wire [7:0] short_do, long_do; - wire [7:0] casc_do, casc2_do; + wire [7:0] casc2_do; reg [7:0] di; reg clear = 0; @@ -19,10 +19,6 @@ module fifo_tb(); (.clk(clk),.rst(rst),.datain(di),.dataout(long_do),.clear(clear), .read(read),.write(write),.full(long_full),.empty(long_empty)); - cascadefifo #(.WIDTH(8), .SIZE(4)) cascadefifo - (.clk(clk),.rst(rst),.datain(di),.dataout(casc_do),.clear(clear), - .read(read),.write(write),.full(casc_full),.empty(casc_empty)); - cascadefifo2 #(.WIDTH(8), .SIZE(4)) cascadefifo2 (.clk(clk),.rst(rst),.datain(di),.dataout(casc2_do),.clear(clear), .read(read),.write(write),.full(casc2_full),.empty(casc2_empty)); |