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author | Josh Blum <josh@joshknows.com> | 2010-01-22 11:56:55 -0800 |
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committer | Josh Blum <josh@joshknows.com> | 2010-01-22 11:56:55 -0800 |
commit | 7bf8a6df381a667134b55701993c6770d32bc76b (patch) | |
tree | 4a298fb5450f7277b5aaf5210740ae18f818c9aa /control_lib/cmdfile | |
parent | 8f2c33eab9396185df259639082b7d1618585973 (diff) | |
download | uhd-7bf8a6df381a667134b55701993c6770d32bc76b.tar.gz uhd-7bf8a6df381a667134b55701993c6770d32bc76b.tar.bz2 uhd-7bf8a6df381a667134b55701993c6770d32bc76b.zip |
Moved usrp2 fpga files into usrp2 subdir.
Diffstat (limited to 'control_lib/cmdfile')
-rw-r--r-- | control_lib/cmdfile | 18 |
1 files changed, 0 insertions, 18 deletions
diff --git a/control_lib/cmdfile b/control_lib/cmdfile deleted file mode 100644 index cb3756cfc..000000000 --- a/control_lib/cmdfile +++ /dev/null @@ -1,18 +0,0 @@ -# My stuff --y . --y ../u2_basic --y ../control_lib --y ../sdr_lib - -# Models --y ../models - -# Open Cores --y ../opencores/spi/rtl/verilog -+incdir+../opencores/spi/rtl/verilog --y ../opencores/wb_conbus/rtl/verilog -+incdir+../opencores/wb_conbus/rtl/verilog --y ../opencores/i2c/rtl/verilog -+incdir+../opencores/i2c/rtl/verilog --y ../opencores/aemb/rtl/verilog --y ../opencores/simple_gpio/rtl |