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author | jcorgan <jcorgan@221aa14e-8319-0410-a670-987f0aec2ac5> | 2008-09-08 01:00:12 +0000 |
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committer | jcorgan <jcorgan@221aa14e-8319-0410-a670-987f0aec2ac5> | 2008-09-08 01:00:12 +0000 |
commit | 61f2f0214c5999ea42a368a4fc99f03d8eb28d1e (patch) | |
tree | e7e24a9adc05ff1422fe3ada9926a51634741b47 /control_lib/clock_control_tb.sav | |
download | uhd-61f2f0214c5999ea42a368a4fc99f03d8eb28d1e.tar.gz uhd-61f2f0214c5999ea42a368a4fc99f03d8eb28d1e.tar.bz2 uhd-61f2f0214c5999ea42a368a4fc99f03d8eb28d1e.zip |
Merged r9433:9527 from features/gr-usrp2 into trunk. Adds usrp2 and gr-usrp2 top-level components. Trunk passes distcheck with mb-gcc installed, but currently not without them. The key issue is that when mb-gcc is not installed, the build system skips over the usrp2/firmware directory, and the firmware include files don't get put into the dist tarball. But we can't do the usual DIST_SUBDIRS method as the firmware is a subpackage.
git-svn-id: http://gnuradio.org/svn/gnuradio/trunk@9528 221aa14e-8319-0410-a670-987f0aec2ac5
Diffstat (limited to 'control_lib/clock_control_tb.sav')
-rw-r--r-- | control_lib/clock_control_tb.sav | 28 |
1 files changed, 28 insertions, 0 deletions
diff --git a/control_lib/clock_control_tb.sav b/control_lib/clock_control_tb.sav new file mode 100644 index 000000000..be4001dc5 --- /dev/null +++ b/control_lib/clock_control_tb.sav @@ -0,0 +1,28 @@ +[size] 1400 971 +[pos] -1 -1 +*-7.848898 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +@28 +clock_control_tb.aux_clk +clock_control_tb.reset +clock_control_tb.sclk +clock_control_tb.sdi +clock_control_tb.sdo +clock_control_tb.sen +@22 +clock_control_tb.clock_control.counter[7:0] +@28 +clock_control_tb.clock_control.done +@22 +clock_control_tb.clock_control.entry[5:0] +@28 +clock_control_tb.clock_control.read +clock_control_tb.clock_control.reset +clock_control_tb.clock_control.sclk +clock_control_tb.clock_control.w[1:0] +clock_control_tb.sen +clock_control_tb.sdo +clock_control_tb.sclk +clock_control_tb.clock_control.done +clock_control_tb.clock_control.start +@22 +clock_control_tb.clock_control.addr_data[20:0] |