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authorjcorgan <jcorgan@221aa14e-8319-0410-a670-987f0aec2ac5>2008-09-08 01:00:12 +0000
committerjcorgan <jcorgan@221aa14e-8319-0410-a670-987f0aec2ac5>2008-09-08 01:00:12 +0000
commit61f2f0214c5999ea42a368a4fc99f03d8eb28d1e (patch)
treee7e24a9adc05ff1422fe3ada9926a51634741b47 /control_lib/cascadefifo.v
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Merged r9433:9527 from features/gr-usrp2 into trunk. Adds usrp2 and gr-usrp2 top-level components. Trunk passes distcheck with mb-gcc installed, but currently not without them. The key issue is that when mb-gcc is not installed, the build system skips over the usrp2/firmware directory, and the firmware include files don't get put into the dist tarball. But we can't do the usual DIST_SUBDIRS method as the firmware is a subpackage.
git-svn-id: http://gnuradio.org/svn/gnuradio/trunk@9528 221aa14e-8319-0410-a670-987f0aec2ac5
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+
+
+// This FIFO exists to provide an intermediate point for the data on its
+// long trek from one RAM (in the buffer pool) to another (in the longfifo)
+// The shortfifo is more flexible in its placement since it is based on
+// distributed RAM
+// This one should only be used on transmit side applications. I.e. tx_mac, tx_dsp, etc.
+// Spartan 3's have slow routing....
+// If we REALLY need to, we could also do this on the output side,
+// with for the receive side stuff
+
+module cascadefifo
+ #(parameter WIDTH=32, SIZE=9)
+ (input clk, input rst,
+ input [WIDTH-1:0] datain,
+ output [WIDTH-1:0] dataout,
+ input read,
+ input write,
+ input clear,
+ output full,
+ output empty,
+ output [15:0] space,
+ output [15:0] occupied);
+
+ wire [WIDTH-1:0] data_int;
+ wire empty_int, full_int, transfer;
+ wire [4:0] short_space, short_occupied;
+ wire [15:0] long_space, long_occupied;
+
+ shortfifo #(.WIDTH(WIDTH)) shortfifo
+ (.clk(clk),.rst(rst),.clear(clear),
+ .datain(datain), .write(write), .full(full),
+ .dataout(data_int), .read(transfer), .empty(empty_int),
+ .space(short_space),.occupied(short_occupied) );
+
+ longfifo #(.WIDTH(WIDTH),.SIZE(SIZE)) longfifo
+ (.clk(clk),.rst(rst),.clear(clear),
+ .datain(data_int), .write(transfer), .full(full_int),
+ .dataout(dataout), .read(read), .empty(empty),
+ .space(long_space),.occupied(long_occupied) );
+
+ assign transfer = ~empty_int & ~full_int;
+
+ assign space = {11'b0,short_space} + long_space;
+ assign occupied = {11'b0,short_occupied} + long_occupied;
+
+endmodule // cascadefifo
+
+
+