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| author | Josh Blum <josh@joshknows.com> | 2010-01-22 11:56:55 -0800 |
|---|---|---|
| committer | Josh Blum <josh@joshknows.com> | 2010-01-22 11:56:55 -0800 |
| commit | 7bf8a6df381a667134b55701993c6770d32bc76b (patch) | |
| tree | 4a298fb5450f7277b5aaf5210740ae18f818c9aa /control_lib/WB_SIM.sav | |
| parent | 8f2c33eab9396185df259639082b7d1618585973 (diff) | |
| download | uhd-7bf8a6df381a667134b55701993c6770d32bc76b.tar.gz uhd-7bf8a6df381a667134b55701993c6770d32bc76b.tar.bz2 uhd-7bf8a6df381a667134b55701993c6770d32bc76b.zip | |
Moved usrp2 fpga files into usrp2 subdir.
Diffstat (limited to 'control_lib/WB_SIM.sav')
| -rw-r--r-- | control_lib/WB_SIM.sav | 47 |
1 files changed, 0 insertions, 47 deletions
diff --git a/control_lib/WB_SIM.sav b/control_lib/WB_SIM.sav deleted file mode 100644 index 467cd35ef..000000000 --- a/control_lib/WB_SIM.sav +++ /dev/null @@ -1,47 +0,0 @@ -[size] 1400 971 -[pos] -1 -1 -*-6.099828 350 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -@28 -wb_sim.wb_rst -wb_sim.wb_clk -@23 -wb_sim.rom_data[47:0] -@22 -wb_sim.rom_addr[15:0] -@28 -wb_sim.start -wb_sim.wb_ack -@22 -wb_sim.wb_adr[15:0] -@28 -wb_sim.wb_cyc -@22 -wb_sim.wb_dat[31:0] -wb_sim.wb_sel[3:0] -@28 -wb_sim.wb_stb -wb_sim.wb_we -@22 -wb_sim.port_output[31:0] -@28 -wb_sim.system_control.POR -wb_sim.system_control.aux_clk -wb_sim.system_control.clk_fpga -@29 -wb_sim.system_control.done -@28 -wb_sim.system_control.dsp_clk -wb_sim.system_control.fin_del1 -wb_sim.system_control.fin_del2 -wb_sim.system_control.fin_del3 -wb_sim.system_control.fin_ret_aux -@29 -wb_sim.system_control.fin_ret_fpga -@28 -wb_sim.system_control.finished -wb_sim.system_control.reset_out -wb_sim.system_control.start -wb_sim.system_control.started -wb_sim.system_control.wb_clk_o -wb_sim.system_control.wb_rst_o -wb_sim.system_control.wb_rst_o_alt |