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| author | Josh Blum <josh@joshknows.com> | 2010-01-22 11:56:55 -0800 |
|---|---|---|
| committer | Josh Blum <josh@joshknows.com> | 2010-01-22 11:56:55 -0800 |
| commit | 7bf8a6df381a667134b55701993c6770d32bc76b (patch) | |
| tree | 4a298fb5450f7277b5aaf5210740ae18f818c9aa /control_lib/SYSCTRL.sav | |
| parent | 8f2c33eab9396185df259639082b7d1618585973 (diff) | |
| download | uhd-7bf8a6df381a667134b55701993c6770d32bc76b.tar.gz uhd-7bf8a6df381a667134b55701993c6770d32bc76b.tar.bz2 uhd-7bf8a6df381a667134b55701993c6770d32bc76b.zip | |
Moved usrp2 fpga files into usrp2 subdir.
Diffstat (limited to 'control_lib/SYSCTRL.sav')
| -rw-r--r-- | control_lib/SYSCTRL.sav | 24 |
1 files changed, 0 insertions, 24 deletions
diff --git a/control_lib/SYSCTRL.sav b/control_lib/SYSCTRL.sav deleted file mode 100644 index 43bfef10e..000000000 --- a/control_lib/SYSCTRL.sav +++ /dev/null @@ -1,24 +0,0 @@ -[size] 1400 971 -[pos] -1 -1 -*-11.026821 2450 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -@28 -system_control_tb.aux_clk -@29 -system_control_tb.clk_fpga -@28 -system_control_tb.dsp_clk -system_control_tb.dsp_rst -system_control_tb.proc_rst -system_control_tb.rl_done -system_control_tb.rl_rst -system_control_tb.wb_clk -system_control_tb.wb_rst -system_control_tb.system_control.POR -@22 -system_control_tb.system_control.POR_ctr[3:0] -@28 -system_control_tb.clock_ready -system_control_tb.system_control.half_clk -system_control_tb.system_control.fin_ret_half -system_control_tb.system_control.fin_ret_aux -system_control_tb.system_control.gate_dsp_clk |