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| author | Toni Jones <toni.jones@ni.com> | 2019-08-26 13:09:04 -0500 |
|---|---|---|
| committer | Aaron Rossetto <aaron.rossetto@ni.com> | 2021-03-04 12:09:52 -0600 |
| commit | 136214240e4275df4d540f058ece2194cec1c7b5 (patch) | |
| tree | 645e8c12dc5924b6ee9ecb45da36be98aa727551 /CODING.md | |
| parent | 1a9033b3e96654dcd374f9d2effe5751b36130f2 (diff) | |
| download | uhd-136214240e4275df4d540f058ece2194cec1c7b5.tar.gz uhd-136214240e4275df4d540f058ece2194cec1c7b5.tar.bz2 uhd-136214240e4275df4d540f058ece2194cec1c7b5.zip | |
mpm: Implement 32 bit register interface with SPI
Implement SPI transfers which are 12 bytes in length to support
access for 32 bit register interfaces. 12 byte transactions are
necessary for Titanium MB PS CPLD SPI transactions. This implementation
supports 48 bits of TX data per transfer and offsets all flags and
data shifts from the end of the TX data portion of the transfer buffer
rather than the end of the entire transfer buffer.
Diffstat (limited to 'CODING.md')
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