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| author | Martin Braun <martin.braun@ettus.com> | 2019-10-15 16:30:01 -0700 |
|---|---|---|
| committer | Martin Braun <martin.braun@ettus.com> | 2019-10-15 16:30:49 -0700 |
| commit | be183dae7a5d2e5f546d699c233d17430dd315ee (patch) | |
| tree | 39f8d6726c634aae668990c3280c7e6d5cc8aac0 /CHANGELOG | |
| parent | 5c0d0834a4eb1da12940196624f707347395855a (diff) | |
| download | uhd-be183dae7a5d2e5f546d699c233d17430dd315ee.tar.gz uhd-be183dae7a5d2e5f546d699c233d17430dd315ee.tar.bz2 uhd-be183dae7a5d2e5f546d699c233d17430dd315ee.zip | |
Update branch for upcoming 3.15 release
- Update submodule pointer
- Update CHANGELOG to incorporate latest changes
Diffstat (limited to 'CHANGELOG')
| -rw-r--r-- | CHANGELOG | 6 |
1 files changed, 4 insertions, 2 deletions
@@ -57,7 +57,8 @@ Change Log for Releases mux data streams over liberio transports (e.g. to require fewer DMA channels on E310), wait for DPDK links to come up before proceeding, relax failure handling when updating components (fixes spurious errors - when updating FPGA images over SFP) + when updating FPGA images over SFP), fix issue where RPC + initialization would hang on failure * FPGA: Use new device-tree overlay syntax, upgraded to Vivado 2018.3, broke various paths with critical timing, allow SystemVerilog source files, improve viv_modify_bd and viv_modify_tcl_bd, fix resets on 2clk @@ -78,7 +79,8 @@ Change Log for Releases from the CMake commandline, add replay example, fix missing 'project', replace ENABLE_PYTHON3 with a simpler Python detection, clean up superfluous modules, improve log statements, bump dependency min - versions, add MPM unit testing, fix missing BIGOBJ for MSVC + versions, add MPM unit testing, fix missing BIGOBJ for MSVC, add our + own UHDBoost.cmake to better find Boost across versions and systems * Formatting: Apply clang-format to all files, break after template<> |