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| author | michael-west <michael.west@ettus.com> | 2019-09-24 17:58:13 -0700 |
|---|---|---|
| committer | Martin Braun <martin.braun@ettus.com> | 2019-10-15 15:21:52 -0700 |
| commit | 5c0d0834a4eb1da12940196624f707347395855a (patch) | |
| tree | f3b9356ad9784fd0a2dbac62a021bb96d0b3c35a /CHANGELOG | |
| parent | b2e042963a7c5474ff0492ed2af393b842cf4c59 (diff) | |
| download | uhd-5c0d0834a4eb1da12940196624f707347395855a.tar.gz uhd-5c0d0834a4eb1da12940196624f707347395855a.tar.bz2 uhd-5c0d0834a4eb1da12940196624f707347395855a.zip | |
Docs: Adjust FPGA functional verification tests
- Reduce long tests from 3600 seconds to 600 seconds.
- Remove 2xRX@153.6e6 test for N310 10 GbE (not practical).
Signed-off-by: michael-west <michael.west@ettus.com>
Diffstat (limited to 'CHANGELOG')
0 files changed, 0 insertions, 0 deletions