Preparing branch for 3.10.1.1 release.

- Updated version string
- Updated fpga-src submodule
- Updated CHANGELOG
- Updated images package

1 files changed, 23 insertions, 0 deletions

diff --git a/CHANGELOG b/CHANGELOG
index 95eff463c..2f9a0c23a 100644
--- a/CHANGELOG
+++ b/CHANGELOG
@@ -1,6 +1,29 @@
 Change Log for Releases
 ==============================
 
+
+## 003.010.002.000
+
+- Docs: The protocol for Gen-3 devices is now consistently referred to as CHDR.
+- X300: Fixed EEPROM corruption bug (happened when two processes would access
+  find routines on the same device at the same time). Improved initialization
+  time. CE clock is now 214 MHz. Fixed channel list generation. Find routines
+  now more lenient in case one devices fails (others can still be found then).
+  Improve PCIe behaviour. Fix timed commands for non-TwinRX dboards. Improve
+  AXI Interconnect (faster, improved build timing).
+- N231: Use second_addr (like X300).
+- C API: Added UHD_VERSION macro. Fixed online rate change.
+- Utils: Minor fixes to uhd_images_downloader.
+- Build/CMake: Fixed some Py3k build issues. Fixed many compiler warnings. Allow
+  to specify package names. 
+- RFNoC: Fixed sampling rate mismatch error. Noc-Shell uses a non-cascaded 2-clk
+  FIFO. Increase default FIFO sizes on DUC and DDC blocks.
+- UBX: Force on RX driver to eliminate transient. 
+- Transport code: Fixed memory leak.
+- FPGA repository: Merged usrp3_rfnoc and usrp3 directories again. Cleaned up
+  superfluous files. Clean separation between Gen-3 and other devices in usrp3.
+
+
 ## 003.010.001.000
 
 - Fixed multiple compiler warnings