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| author | michael-west <michael.west@ettus.com> | 2014-03-26 15:59:30 -0700 |
|---|---|---|
| committer | michael-west <michael.west@ettus.com> | 2014-03-26 15:59:30 -0700 |
| commit | 72bcea366a866ead85f9883d06475516ac64a850 (patch) | |
| tree | cd30fbd984a294b54075f79282d060f7b73a078c | |
| parent | 04292f9b109479b639add31f83fd240a6387f488 (diff) | |
| download | uhd-72bcea366a866ead85f9883d06475516ac64a850.tar.gz uhd-72bcea366a866ead85f9883d06475516ac64a850.tar.bz2 uhd-72bcea366a866ead85f9883d06475516ac64a850.zip | |
Changed all references to Catalina to AD9361
| -rw-r--r-- | host/docs/usrp_b200.rst | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/host/docs/usrp_b200.rst b/host/docs/usrp_b200.rst index 1b0d7b719..3fd9dacb5 100644 --- a/host/docs/usrp_b200.rst +++ b/host/docs/usrp_b200.rst @@ -165,7 +165,7 @@ Component ID Description Details J603 Upstream Voltage Regulation | 3.3 V supply Test Point | Pin 1 - 3.7 V | Pin 2 - gnd - J604 Catalina Supply Test Point | Pin 1 - 1.3 V + J604 AD9361 Supply Test Point | Pin 1 - 1.3 V | Pin 2 - gnd J605 FPGA Supply Test Point | Pin 1 - 1.2 V | Pin 2 - gnd @@ -176,12 +176,12 @@ Component ID Description Details | Pin 2 - gnd T600 External Voltage Supply Test Point - T601 1.3 V Catalina Power Good + T601 1.3 V AD9361 Power Good Test Point - T602 1.3 V Catalina Synthesizer + T602 1.3 V AD9361 Synthesizer Power Good Test Point - TP302 Catalina AUX DAC1 Test Point - TP303 Catalina AUX DAC2 Test Point + TP302 AD9361 AUX DAC1 Test Point + TP303 AD9361 AUX DAC2 Test Point T700 Not connected T701 Not connected T702 FX3 External Clock In | Not used |