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authorAshish Chaudhari <ashish@ettus.com>2014-08-19 12:05:46 -0700
committerAshish Chaudhari <ashish@ettus.com>2014-08-19 12:05:46 -0700
commit3347e831f002da769632dfe0c70ea17c2d749a8a (patch)
tree2f0709264061d440cf24c8060478f0344e41c1a1
parenta38fee789d66b87b9e25edcfcf47247fe11f8371 (diff)
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fpga: Added FPGA code for X300 MIMO alignment bugfix
-rw-r--r--fpga/usrp3/top/x300/Makefile.x300.inc7
-rw-r--r--fpga/usrp3/top/x300/bus_int.v2
-rw-r--r--fpga/usrp3/top/x300/capture_ddrlvds.v54
-rw-r--r--fpga/usrp3/top/x300/timing.ucf5
-rw-r--r--fpga/usrp3/top/x300/x300.v4
5 files changed, 22 insertions, 50 deletions
diff --git a/fpga/usrp3/top/x300/Makefile.x300.inc b/fpga/usrp3/top/x300/Makefile.x300.inc
index 1395b5f00..6e13e4fed 100644
--- a/fpga/usrp3/top/x300/Makefile.x300.inc
+++ b/fpga/usrp3/top/x300/Makefile.x300.inc
@@ -49,7 +49,7 @@ synthesis_tool "XST (VHDL/Verilog)" \
simulator "ISim (VHDL/Verilog)" \
"Preferred Language" "Verilog" \
"Enable Message Filtering" FALSE \
-"Display Incremental Messages" FALSE
+"Display Incremental Messages" FALSE
##################################################
# Sources
@@ -142,7 +142,8 @@ MAP_PROPERTIES = \
"Map Effort Level" High \
"Extra Effort" Normal \
"Perform Timing-Driven Packing and Placement" TRUE \
-"Enable Multi-Threading 2"
+"Enable Multi-Threading 2" \
+"Starting Placer Cost Table (1-100)" $$(( $$RANDOM % 100 + 1 ))
#"Map to Input Functions" 4 \
PLACE_ROUTE_PROPERTIES = \
@@ -160,6 +161,6 @@ GEN_PROG_FILE_PROPERTIES = \
"Done (Output Events)" 5 \
"Enable Bitstream Compression" FALSE \
"Enable Outputs (Output Events)" 6 \
-"Wait for DCI Match (Output Events)" NoWait
+"Wait for DCI Match (Output Events)" NoWait
SIM_MODEL_PROPERTIES = ""
diff --git a/fpga/usrp3/top/x300/bus_int.v b/fpga/usrp3/top/x300/bus_int.v
index 416b327bb..38991dad6 100644
--- a/fpga/usrp3/top/x300/bus_int.v
+++ b/fpga/usrp3/top/x300/bus_int.v
@@ -141,7 +141,7 @@ module bus_int
localparam RB_BIST = 8'd128;
- localparam COMPAT_MAJOR = 16'h0006;
+ localparam COMPAT_MAJOR = 16'h0007;
localparam COMPAT_MINOR = 16'h0000;
wire [31:0] set_data;
diff --git a/fpga/usrp3/top/x300/capture_ddrlvds.v b/fpga/usrp3/top/x300/capture_ddrlvds.v
index 193caf6e1..308171fc7 100644
--- a/fpga/usrp3/top/x300/capture_ddrlvds.v
+++ b/fpga/usrp3/top/x300/capture_ddrlvds.v
@@ -1,25 +1,26 @@
//
-// Copyright 2011 Ettus Research LLC
+// Copyright 2011-2014 Ettus Research LLC
//
-
-
+// The two clocks are aligned externally in order to eliminate the need for a FIFO.
+// A FIFO cannot be used to transition between clock domains because it can cause
+// alignment issues between the output of multiple modules.
module capture_ddrlvds
#(parameter WIDTH=7,
parameter X300=0)
(input clk,
- input reset,
input ssclk_p,
input ssclk_n,
input [WIDTH-1:0] in_p,
input [WIDTH-1:0] in_n,
- output [(2*WIDTH)-1:0] out);
+ output reg [(2*WIDTH)-1:0] out);
wire [WIDTH-1:0] ddr_dat;
wire ssclk;
wire [(2*WIDTH)-1:0] out_pre1;
- wire ssclk_bufio1, ssclk_bufio2, ssclk_bufr, ssclk_bufmr;
+ reg [(2*WIDTH)-1:0] out_pre2;
+ wire ssclk_bufio1, ssclk_bufio2, ssclk_bufmr;
IBUFGDS #(.DIFF_TERM("TRUE"))
clkbuf (.O(ssclk), .I(ssclk_p), .IB(ssclk_n));
@@ -33,20 +34,12 @@ module capture_ddrlvds
.I(ssclk_bufmr),
.O(ssclk_bufio1)
);
+
BUFIO clkbufio2 (
.I(ssclk_bufmr),
.O(ssclk_bufio2)
);
- BUFR
- #(.SIM_DEVICE("7SERIES"),
- .BUFR_DIVIDE("BYPASS"))
- clkbufr (
- .I(ssclk_bufmr),
- .O(ssclk_bufr)
- );
-
-
genvar i;
generate
@@ -68,34 +61,7 @@ module capture_ddrlvds
end
endgenerate
-
-
- reg rd_en;
- wire full, empty, almost_empty;
-
-
- input_sample_fifo input_sample_fifo_i
- (
- .rst(reset), // input rst
- .wr_clk(ssclk_bufr), // input wr_clk
- .rd_clk(clk), // input rd_clk
- .din(out_pre1), // input [27 : 0] din
- .wr_en(1'b1), // input wr_en
- .rd_en(rd_en), // input rd_en
- .dout(out), // output [27 : 0] dout
- .full(full), // output full
- .empty(empty), // output empty
- .almost_empty(almost_empty) // output almost_empty
- );
-
-
- always @(posedge clk) begin
- if (reset)
- rd_en <= 0;
- else if (~almost_empty)
- rd_en <= 1;
- else if (empty)
- rd_en <= 0;
- end
+ always @(posedge clk)
+ {out, out_pre2} <= {out_pre2, out_pre1};
endmodule // capture_ddrlvds
diff --git a/fpga/usrp3/top/x300/timing.ucf b/fpga/usrp3/top/x300/timing.ucf
index a84a92a63..b638b2c99 100644
--- a/fpga/usrp3/top/x300/timing.ucf
+++ b/fpga/usrp3/top/x300/timing.ucf
@@ -34,3 +34,8 @@ TIMESPEC TS_IOPORT2_CLK_TO_BUS_CLK_FALEPATH = FROM ioport2_clk_grp TO bus_clk_gr
TIMESPEC TS_IOPORT2_CLK_TO_RIO40_CLK_FALEPATH = FROM ioport2_clk_grp TO rio40_clk_grp TIG;
TIMESPEC TS_RIO40_CLK_TO_IOPORT2_CLK_FALEPATH = FROM rio40_clk_grp TO ioport2_clk_grp TIG;
+# FPGA_CLK_p/n is externally phase shifted to allow for crossing from the ADC clock domain
+# to the radio_clk (aka FPGA_CLK_p/n) clock domain. To ensure this timing is consistent,
+# lock the locations of the MMCM and BUFG to generate radio_clk.
+INST "radio_clk_gen/mmcm_adv_inst" LOC = MMCME2_ADV_X0Y0;
+INST "radio_clk_gen/clkout1_buf" LOC = BUFGCTRL_X0Y8; \ No newline at end of file
diff --git a/fpga/usrp3/top/x300/x300.v b/fpga/usrp3/top/x300/x300.v
index e9191a481..e57ae7b3b 100644
--- a/fpga/usrp3/top/x300/x300.v
+++ b/fpga/usrp3/top/x300/x300.v
@@ -484,7 +484,7 @@ module x300
// so I gets a double negative, and is unchanged. Q must be inverted.
capture_ddrlvds #(.WIDTH(14),.X300(1)) cap_db0
- (.clk(radio_clk), .reset(radio_rst), .ssclk_p(DB0_ADC_DCLK_P), .ssclk_n(DB0_ADC_DCLK_N),
+ (.clk(radio_clk), .ssclk_p(DB0_ADC_DCLK_P), .ssclk_n(DB0_ADC_DCLK_N),
.in_p({{DB0_ADC_DA6_P, DB0_ADC_DA5_P, DB0_ADC_DA4_P, DB0_ADC_DA3_P, DB0_ADC_DA2_P, DB0_ADC_DA1_P, DB0_ADC_DA0_P},
{DB0_ADC_DB6_P, DB0_ADC_DB5_P, DB0_ADC_DB4_P, DB0_ADC_DB3_P, DB0_ADC_DB2_P, DB0_ADC_DB1_P, DB0_ADC_DB0_P}}),
@@ -494,7 +494,7 @@ module x300
assign rx0[31:0] = { rx0_i, 2'b00, ~rx0_q_inv, 2'b00 };
capture_ddrlvds #(.WIDTH(14),.X300(1)) cap_db1
- (.clk(radio_clk), .reset(radio_rst), .ssclk_p(DB1_ADC_DCLK_P), .ssclk_n(DB1_ADC_DCLK_N),
+ (.clk(radio_clk), .ssclk_p(DB1_ADC_DCLK_P), .ssclk_n(DB1_ADC_DCLK_N),
.in_p({{DB1_ADC_DA6_P, DB1_ADC_DA5_P, DB1_ADC_DA4_P, DB1_ADC_DA3_P, DB1_ADC_DA2_P, DB1_ADC_DA1_P, DB1_ADC_DA0_P},
{DB1_ADC_DB6_P, DB1_ADC_DB5_P, DB1_ADC_DB4_P, DB1_ADC_DB3_P, DB1_ADC_DB2_P, DB1_ADC_DB1_P, DB1_ADC_DB0_P}}),