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authorJosh Blum <josh@joshknows.com>2013-08-16 10:49:03 -0700
committerJosh Blum <josh@joshknows.com>2013-08-16 10:49:03 -0700
commit9c3fd671810abf0d39d7baa78073b90b95d9b5bc (patch)
treeb01c521d446e28c4df1054198ea7baa149014bf0
parentcacc3fc99468373ff8c576a41dfa6f8f052a68d9 (diff)
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b200: lower clock rate is 5MHz due to DCM
-rw-r--r--host/docs/usrp_b200.rst2
-rw-r--r--host/lib/usrp/common/ad9361_ctrl.hpp3
2 files changed, 3 insertions, 2 deletions
diff --git a/host/docs/usrp_b200.rst b/host/docs/usrp_b200.rst
index 96bf9b5bc..bb2a2876a 100644
--- a/host/docs/usrp_b200.rst
+++ b/host/docs/usrp_b200.rst
@@ -53,7 +53,7 @@ Changing the Master Clock Rate
------------------------------------------------------------------------
The master clock rate feeds the RF frontends and the DSP chains.
Users may select non-default clock rates to acheive integer decimations or interpolations in the DSP chains.
-The default master clock rate defaults to 32 MHz, but can be set to any rate between 220 kHz and 61.44 MHz.
+The default master clock rate defaults to 32 MHz, but can be set to any rate between 5 MHz and 61.44 MHz.
The user can set the master clock rate through the usrp API call set_master_clock_rate(),
or the clock rate can be set through the device arguments, which many applications take:
diff --git a/host/lib/usrp/common/ad9361_ctrl.hpp b/host/lib/usrp/common/ad9361_ctrl.hpp
index e678ba3b0..fd8012764 100644
--- a/host/lib/usrp/common/ad9361_ctrl.hpp
+++ b/host/lib/usrp/common/ad9361_ctrl.hpp
@@ -99,7 +99,8 @@ public:
//! get the clock rate range for the frontend
static uhd::meta_range_t get_clock_rate_range(void)
{
- return uhd::meta_range_t(220e3, 61.44e6);
+ //return uhd::meta_range_t(220e3, 61.44e6);
+ return uhd::meta_range_t(5e6, 61.44e6); //5 MHz DCM low end
}
//! set the filter bandwidth for the frontend