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| author | Josh Blum <josh@joshknows.com> | 2012-02-04 15:12:03 -0800 |
|---|---|---|
| committer | Josh Blum <josh@joshknows.com> | 2012-02-04 15:12:03 -0800 |
| commit | 89ce89c9aca6daf7e293b80c70e14a3e2710e137 (patch) | |
| tree | ebb119eef9859fbbf81205ea3f4aa9f814c1ce51 | |
| parent | 1b489be22ca07a949a9bea59f0040c0c3d770d8a (diff) | |
| download | uhd-89ce89c9aca6daf7e293b80c70e14a3e2710e137.tar.gz uhd-89ce89c9aca6daf7e293b80c70e14a3e2710e137.tar.bz2 uhd-89ce89c9aca6daf7e293b80c70e14a3e2710e137.zip | |
b100: timing constraints on GPIF lines
| -rw-r--r-- | usrp2/top/B100/timing.ucf | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/usrp2/top/B100/timing.ucf b/usrp2/top/B100/timing.ucf index b2a455f6d..96c47cf2c 100644 --- a/usrp2/top/B100/timing.ucf +++ b/usrp2/top/B100/timing.ucf @@ -3,3 +3,12 @@ TIMESPEC "TS_CLK_FPGA_P" = PERIOD "CLK_FPGA_P" 15625 ps HIGH 50 %; NET "IFCLK" TNM_NET = "IFCLK"; TIMESPEC "TS_IFCLK" = PERIOD "IFCLK" 20833 ps HIGH 50 %; + +#constrain FX2 IO +NET "GPIF_D<*>" MAXDELAY = 5.5 ns; +NET "GPIF_CTL<*>" MAXDELAY = 5.5 ns; +NET "GPIF_ADR<*>" MAXDELAY = 5.5ns; +NET "GPIF_SLWR" MAXDELAY = 5.5 ns; +NET "GPIF_SLRD" MAXDELAY = 5.5 ns; +NET "GPIF_SLOE" MAXDELAY = 5.5 ns; +NET "GPIF_PKTEND" MAXDELAY = 5.5 ns; |