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| author | Nick Foster <nick@ettus.com> | 2012-04-24 21:57:52 -0700 |
|---|---|---|
| committer | Nick Foster <nick@ettus.com> | 2012-04-24 21:57:52 -0700 |
| commit | 70db8e9d1c76c2e135695f644da8101853dbcc86 (patch) | |
| tree | b908cf67b8136ba7dba473b711986fea7c61546e | |
| parent | 8a00096f9897fc6bb62e8fb7a5ce2fe336f91a8c (diff) | |
| download | uhd-70db8e9d1c76c2e135695f644da8101853dbcc86.tar.gz uhd-70db8e9d1c76c2e135695f644da8101853dbcc86.tar.bz2 uhd-70db8e9d1c76c2e135695f644da8101853dbcc86.zip | |
slave_fifo: use 2KB FIFO size instead of 1KB
| -rw-r--r-- | usrp2/gpif/slave_fifo.v | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/usrp2/gpif/slave_fifo.v b/usrp2/gpif/slave_fifo.v index 090b7b747..d1a0a027b 100644 --- a/usrp2/gpif/slave_fifo.v +++ b/usrp2/gpif/slave_fifo.v @@ -310,7 +310,7 @@ module slave_fifo wire [15:0] rxfifospace; //deep 36 bit wide input fifo buffers from DSP - fifo_cascade #(.WIDTH(36), .SIZE(8)) rx_fifo36 + fifo_cascade #(.WIDTH(36), .SIZE(9)) rx_fifo36 (.clk(fifo_clk), .reset(fifo_rst), .clear(clear_rx), .datain(rx_data_i), .src_rdy_i(rx_src_rdy_i), .dst_rdy_o(rx_dst_rdy_o), .dataout(rx36_data), .src_rdy_o(rx36_src_rdy), .dst_rdy_i(rx36_dst_rdy)); |